69 lines
1.4 KiB
Verilog
69 lines
1.4 KiB
Verilog
module scanlines #(parameter v2=0)
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(
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input clk,
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input [1:0] scanlines,
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input [23:0] din,
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input hs_in,vs_in,
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input de_in,ce_in,
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output reg [23:0] dout,
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output reg hs_out,vs_out,
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output reg de_out,ce_out
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);
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reg [1:0] scanline;
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always @(posedge clk) begin
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reg old_hs, old_vs;
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old_hs <= hs_in;
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old_vs <= vs_in;
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if(old_hs && ~hs_in) begin
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if(v2) begin
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scanline <= scanline + 1'd1;
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if (scanline == scanlines) scanline <= 0;
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end
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else scanline <= scanline ^ scanlines;
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end
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if(old_vs && ~vs_in) scanline <= 0;
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end
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wire [7:0] r,g,b;
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assign {r,g,b} = din;
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reg [23:0] d;
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always @(*) begin
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case(scanline)
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1: // reduce 25% = 1/2 + 1/4
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d = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
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{1'b0, g[7:1]} + {2'b00, g[7:2]},
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{1'b0, b[7:1]} + {2'b00, b[7:2]}};
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2: // reduce 50% = 1/2
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d = {{1'b0, r[7:1]},
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{1'b0, g[7:1]},
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{1'b0, b[7:1]}};
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3: // reduce 75% = 1/4
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d = {{2'b00, r[7:2]},
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{2'b00, g[7:2]},
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{2'b00, b[7:2]}};
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default: d = {r,g,b};
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endcase
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end
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always @(posedge clk) begin
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reg [23:0] dout1, dout2;
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reg de1,de2,vs1,vs2,hs1,hs2,ce1,ce2;
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dout <= dout2; dout2 <= dout1; dout1 <= d;
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vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in;
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hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in;
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de_out <= de2; de2 <= de1; de1 <= de_in;
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ce_out <= ce2; ce2 <= ce1; ce1 <= ce_in;
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end
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endmodule
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