137 lines
3.5 KiB
Systemverilog
137 lines
3.5 KiB
Systemverilog
module shadowmask
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(
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input clk,
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input clk_sys,
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input cmd_wr,
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input [15:0] cmd_in,
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input [23:0] din,
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input hs_in,vs_in,
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input de_in,
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input brd_in,
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input enable,
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output reg [23:0] dout,
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output reg hs_out,vs_out,
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output reg de_out
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);
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reg [4:0] hmax;
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reg [4:0] vmax;
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reg [7:0] mask_idx;
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reg mask_2x;
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reg mask_rotate;
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reg mask_enable;
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reg [10:0] mask_lut[256];
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always @(posedge clk) begin
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reg [4:0] hcount;
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reg [4:0] vcount;
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reg [3:0] hindex;
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reg [3:0] vindex;
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reg [4:0] hmax2;
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reg [4:0] vmax2;
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reg [11:0] pcnt,pde;
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reg old_hs, old_vs, old_brd;
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reg next_v;
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old_hs <= hs_in;
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old_vs <= vs_in;
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old_brd<= brd_in;
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// hcount and vcount counts pixel rows and columns
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// hindex and vindex half the value of the counters for double size patterns
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// hindex2, vindex2 swap the h and v counters for drawing rotated masks
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hindex <= mask_2x ? hcount[4:1] : hcount[3:0];
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vindex <= mask_2x ? vcount[4:1] : vcount[3:0];
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mask_idx <= mask_rotate ? {hindex,vindex} : {vindex,hindex};
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// hmax and vmax store these sizes
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// hmax2 and vmax2 swap the values to handle rotation
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hmax2 <= ((mask_rotate ? vmax : hmax) << mask_2x) | mask_2x;
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vmax2 <= ((mask_rotate ? hmax : vmax) << mask_2x) | mask_2x;
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pcnt <= pcnt+1'd1;
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if(old_brd && ~brd_in) pde <= pcnt-4'd3;
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hcount <= hcount+1'b1;
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if(hcount == hmax2 || pde == pcnt) hcount <= 0;
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if(~old_brd && brd_in) next_v <= 1;
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if(old_vs && ~vs_in) vcount <= 0;
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if(old_hs && ~hs_in) begin
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vcount <= vcount + next_v;
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next_v <= 0;
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pcnt <= 0;
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if (vcount == vmax2) vcount <= 0;
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end
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end
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reg [4:0] r_mul, g_mul, b_mul; // 1.4 fixed point multipliers
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always @(posedge clk) begin
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reg [10:0] lut;
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lut <= mask_lut[mask_idx];
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r_mul <= 5'b10000; g_mul <= 5'b10000; b_mul <= 5'b10000; // default 100% to all channels
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if (mask_enable) begin
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r_mul <= lut[10] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
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g_mul <= lut[9] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
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b_mul <= lut[8] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
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end
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end
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always @(posedge clk) begin
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reg [11:0] vid;
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reg [7:0] r1, g1, b1;
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reg [7:0] r2, g2, b2;
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reg [7:0] r3_x, g3_x, b3_x; // 6.25% + 12.5%
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reg [8:0] r3_y, g3_y, b3_y; // 25% + 50% + 100%
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reg [8:0] r4, g4, b4;
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// C1 - data input
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{r1,g1,b1} <= din;
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vid <= {vid[8:0],vs_in, hs_in, de_in};
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// C2 - relax timings
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{r2,g2,b2} <= {r1,g1,b1};
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// C3 - perform multiplications
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r3_x <= ({4{r_mul[0]}} & r2[7:4]) + ({8{r_mul[1]}} & r2[7:3]);
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r3_y <= ({6{r_mul[2]}} & r2[7:2]) + ({7{r_mul[3]}} & r2[7:1]) + ({9{r_mul[4]}} & r2[7:0]);
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g3_x <= ({4{g_mul[0]}} & g2[7:4]) + ({8{g_mul[1]}} & g2[7:3]);
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g3_y <= ({6{g_mul[2]}} & g2[7:2]) + ({7{g_mul[3]}} & g2[7:1]) + ({9{g_mul[4]}} & g2[7:0]);
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b3_x <= ({4{b_mul[0]}} & b2[7:4]) + ({8{b_mul[1]}} & b2[7:3]);
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b3_y <= ({6{b_mul[2]}} & b2[7:2]) + ({7{b_mul[3]}} & b2[7:1]) + ({9{b_mul[4]}} & b2[7:0]);
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// C4 - combine results
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r4 <= r3_x + r3_y;
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g4 <= g3_x + g3_y;
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b4 <= b3_x + b3_y;
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// C5 - clamp and output
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dout <= {{8{r4[8]}} | r4[7:0], {8{g4[8]}} | g4[7:0], {8{b4[8]}} | b4[7:0]};
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{vs_out,hs_out,de_out} <= vid[11:9];
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end
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// clock in mask commands
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always @(posedge clk_sys) begin
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reg m_enable;
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reg [7:0] idx;
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if (cmd_wr) begin
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case(cmd_in[15:13])
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3'b000: begin {m_enable, mask_rotate, mask_2x} <= cmd_in[3:1]; idx <= 0; end
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3'b001: vmax <= cmd_in[3:0];
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3'b010: hmax <= cmd_in[3:0];
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3'b011: begin mask_lut[idx] <= cmd_in[10:0]; idx <= idx + 1'd1; end
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endcase
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end
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mask_enable <= m_enable & enable;
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end
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endmodule
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