34 lines
934 B
Verilog
34 lines
934 B
Verilog
//
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// PWM DAC
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//
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// MSBI is the highest bit number. NOT amount of bits!
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//
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module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1)
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(
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output reg DACout, //Average Output feeding analog lowpass
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input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
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input CLK,
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input RESET
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);
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reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
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reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
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reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
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reg [MSBI+2:0] DeltaB; //B input of Delta Adder
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always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
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always @(*) DeltaAdder = DACin + DeltaB;
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always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
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always @(posedge CLK or posedge RESET) begin
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if(RESET) begin
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SigmaLatch <= 1'b1 << (MSBI+1);
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DACout <= INV;
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end else begin
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SigmaLatch <= SigmaAdder;
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DACout <= SigmaLatch[MSBI+2] ^ INV;
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end
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end
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endmodule
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