571 lines
16 KiB
Systemverilog
571 lines
16 KiB
Systemverilog
`timescale 1 ps / 1 ps
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module sysmem_lite
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(
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output clock,
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output reset_out,
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input reset_hps_cold_req,
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input reset_hps_warm_req,
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input reset_core_req,
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input ram1_clk,
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input [28:0] ram1_address,
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input [7:0] ram1_burstcount,
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output ram1_waitrequest,
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output [63:0] ram1_readdata,
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output ram1_readdatavalid,
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input ram1_read,
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input [63:0] ram1_writedata,
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input [7:0] ram1_byteenable,
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input ram1_write,
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input ram2_clk,
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input [28:0] ram2_address,
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input [7:0] ram2_burstcount,
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output ram2_waitrequest,
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output [63:0] ram2_readdata,
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output ram2_readdatavalid,
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input ram2_read,
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input [63:0] ram2_writedata,
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input [7:0] ram2_byteenable,
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input ram2_write,
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input vbuf_clk,
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input [27:0] vbuf_address,
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input [7:0] vbuf_burstcount,
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output vbuf_waitrequest,
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output [127:0] vbuf_readdata,
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output vbuf_readdatavalid,
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input vbuf_read,
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input [127:0] vbuf_writedata,
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input [15:0] vbuf_byteenable,
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input vbuf_write
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);
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assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req;
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////////////////////////////////////////////////////////
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//// f2sdram_safe_terminator_ram1 ////
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////////////////////////////////////////////////////////
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wire [28:0] f2h_ram1_address;
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wire [7:0] f2h_ram1_burstcount;
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wire f2h_ram1_waitrequest;
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wire [63:0] f2h_ram1_readdata;
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wire f2h_ram1_readdatavalid;
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wire f2h_ram1_read;
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wire [63:0] f2h_ram1_writedata;
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wire [7:0] f2h_ram1_byteenable;
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wire f2h_ram1_write;
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_0 = 1'b1;
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_1 = 1'b1;
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always @(posedge ram1_clk) begin
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ram1_reset_0 <= reset_out;
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ram1_reset_1 <= ram1_reset_0;
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end
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f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram1
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(
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.clk (ram1_clk),
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.rst_req_sync (ram1_reset_1),
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.waitrequest_slave (ram1_waitrequest),
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.burstcount_slave (ram1_burstcount),
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.address_slave (ram1_address),
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.readdata_slave (ram1_readdata),
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.readdatavalid_slave (ram1_readdatavalid),
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.read_slave (ram1_read),
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.writedata_slave (ram1_writedata),
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.byteenable_slave (ram1_byteenable),
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.write_slave (ram1_write),
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.waitrequest_master (f2h_ram1_waitrequest),
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.burstcount_master (f2h_ram1_burstcount),
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.address_master (f2h_ram1_address),
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.readdata_master (f2h_ram1_readdata),
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.readdatavalid_master (f2h_ram1_readdatavalid),
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.read_master (f2h_ram1_read),
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.writedata_master (f2h_ram1_writedata),
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.byteenable_master (f2h_ram1_byteenable),
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.write_master (f2h_ram1_write)
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);
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////////////////////////////////////////////////////////
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//// f2sdram_safe_terminator_ram2 ////
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////////////////////////////////////////////////////////
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wire [28:0] f2h_ram2_address;
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wire [7:0] f2h_ram2_burstcount;
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wire f2h_ram2_waitrequest;
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wire [63:0] f2h_ram2_readdata;
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wire f2h_ram2_readdatavalid;
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wire f2h_ram2_read;
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wire [63:0] f2h_ram2_writedata;
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wire [7:0] f2h_ram2_byteenable;
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wire f2h_ram2_write;
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_0 = 1'b1;
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_1 = 1'b1;
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always @(posedge ram2_clk) begin
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ram2_reset_0 <= reset_out;
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ram2_reset_1 <= ram2_reset_0;
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end
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f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram2
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(
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.clk (ram2_clk),
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.rst_req_sync (ram2_reset_1),
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.waitrequest_slave (ram2_waitrequest),
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.burstcount_slave (ram2_burstcount),
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.address_slave (ram2_address),
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.readdata_slave (ram2_readdata),
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.readdatavalid_slave (ram2_readdatavalid),
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.read_slave (ram2_read),
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.writedata_slave (ram2_writedata),
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.byteenable_slave (ram2_byteenable),
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.write_slave (ram2_write),
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.waitrequest_master (f2h_ram2_waitrequest),
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.burstcount_master (f2h_ram2_burstcount),
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.address_master (f2h_ram2_address),
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.readdata_master (f2h_ram2_readdata),
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.readdatavalid_master (f2h_ram2_readdatavalid),
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.read_master (f2h_ram2_read),
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.writedata_master (f2h_ram2_writedata),
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.byteenable_master (f2h_ram2_byteenable),
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.write_master (f2h_ram2_write)
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);
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////////////////////////////////////////////////////////
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//// f2sdram_safe_terminator_vbuf ////
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////////////////////////////////////////////////////////
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wire [27:0] f2h_vbuf_address;
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wire [7:0] f2h_vbuf_burstcount;
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wire f2h_vbuf_waitrequest;
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wire [127:0] f2h_vbuf_readdata;
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wire f2h_vbuf_readdatavalid;
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wire f2h_vbuf_read;
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wire [127:0] f2h_vbuf_writedata;
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wire [15:0] f2h_vbuf_byteenable;
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wire f2h_vbuf_write;
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_0 = 1'b1;
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_1 = 1'b1;
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always @(posedge vbuf_clk) begin
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vbuf_reset_0 <= reset_out;
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vbuf_reset_1 <= vbuf_reset_0;
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end
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f2sdram_safe_terminator #(128, 8) f2sdram_safe_terminator_vbuf
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(
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.clk (vbuf_clk),
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.rst_req_sync (vbuf_reset_1),
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.waitrequest_slave (vbuf_waitrequest),
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.burstcount_slave (vbuf_burstcount),
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.address_slave (vbuf_address),
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.readdata_slave (vbuf_readdata),
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.readdatavalid_slave (vbuf_readdatavalid),
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.read_slave (vbuf_read),
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.writedata_slave (vbuf_writedata),
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.byteenable_slave (vbuf_byteenable),
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.write_slave (vbuf_write),
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.waitrequest_master (f2h_vbuf_waitrequest),
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.burstcount_master (f2h_vbuf_burstcount),
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.address_master (f2h_vbuf_address),
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.readdata_master (f2h_vbuf_readdata),
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.readdatavalid_master (f2h_vbuf_readdatavalid),
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.read_master (f2h_vbuf_read),
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.writedata_master (f2h_vbuf_writedata),
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.byteenable_master (f2h_vbuf_byteenable),
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.write_master (f2h_vbuf_write)
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);
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////////////////////////////////////////////////////////
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//// HPS <> FPGA interfaces ////
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////////////////////////////////////////////////////////
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sysmem_HPS_fpga_interfaces fpga_interfaces (
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.f2h_cold_rst_req_n (~reset_hps_cold_req),
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.f2h_warm_rst_req_n (~reset_hps_warm_req),
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.h2f_user0_clk (clock),
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.h2f_rst_n (hps_h2f_reset_n),
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.f2h_sdram0_clk (vbuf_clk),
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.f2h_sdram0_ADDRESS (f2h_vbuf_address),
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.f2h_sdram0_BURSTCOUNT (f2h_vbuf_burstcount),
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.f2h_sdram0_WAITREQUEST (f2h_vbuf_waitrequest),
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.f2h_sdram0_READDATA (f2h_vbuf_readdata),
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.f2h_sdram0_READDATAVALID (f2h_vbuf_readdatavalid),
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.f2h_sdram0_READ (f2h_vbuf_read),
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.f2h_sdram0_WRITEDATA (f2h_vbuf_writedata),
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.f2h_sdram0_BYTEENABLE (f2h_vbuf_byteenable),
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.f2h_sdram0_WRITE (f2h_vbuf_write),
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.f2h_sdram1_clk (ram1_clk),
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.f2h_sdram1_ADDRESS (f2h_ram1_address),
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.f2h_sdram1_BURSTCOUNT (f2h_ram1_burstcount),
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.f2h_sdram1_WAITREQUEST (f2h_ram1_waitrequest),
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.f2h_sdram1_READDATA (f2h_ram1_readdata),
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.f2h_sdram1_READDATAVALID (f2h_ram1_readdatavalid),
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.f2h_sdram1_READ (f2h_ram1_read),
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.f2h_sdram1_WRITEDATA (f2h_ram1_writedata),
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.f2h_sdram1_BYTEENABLE (f2h_ram1_byteenable),
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.f2h_sdram1_WRITE (f2h_ram1_write),
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.f2h_sdram2_clk (ram2_clk),
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.f2h_sdram2_ADDRESS (f2h_ram2_address),
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.f2h_sdram2_BURSTCOUNT (f2h_ram2_burstcount),
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.f2h_sdram2_WAITREQUEST (f2h_ram2_waitrequest),
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.f2h_sdram2_READDATA (f2h_ram2_readdata),
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.f2h_sdram2_READDATAVALID (f2h_ram2_readdatavalid),
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.f2h_sdram2_READ (f2h_ram2_read),
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.f2h_sdram2_WRITEDATA (f2h_ram2_writedata),
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.f2h_sdram2_BYTEENABLE (f2h_ram2_byteenable),
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.f2h_sdram2_WRITE (f2h_ram2_write)
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);
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wire hps_h2f_reset_n;
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reg init_reset_n = 0;
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always @(posedge clock) begin
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integer timeout = 0;
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if(timeout < 2000000) begin
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init_reset_n <= 0;
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timeout <= timeout + 1;
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end
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else init_reset_n <= 1;
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end
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endmodule
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module sysmem_HPS_fpga_interfaces
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(
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// h2f_reset
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output wire [1 - 1 : 0 ] h2f_rst_n
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// f2h_cold_reset_req
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,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
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// f2h_warm_reset_req
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,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
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// h2f_user0_clock
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,output wire [1 - 1 : 0 ] h2f_user0_clk
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// f2h_sdram0_data
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,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
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,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
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,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
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,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
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,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
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,input wire [1 - 1 : 0 ] f2h_sdram0_READ
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,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
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,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
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,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
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// f2h_sdram0_clock
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,input wire [1 - 1 : 0 ] f2h_sdram0_clk
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// f2h_sdram1_data
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,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
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,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
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,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
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,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
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,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
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,input wire [1 - 1 : 0 ] f2h_sdram1_READ
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,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
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,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
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,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
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// f2h_sdram1_clock
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,input wire [1 - 1 : 0 ] f2h_sdram1_clk
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// f2h_sdram2_data
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,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
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,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
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,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
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,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
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,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
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,input wire [1 - 1 : 0 ] f2h_sdram2_READ
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,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
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,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
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,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
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// f2h_sdram2_clock
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,input wire [1 - 1 : 0 ] f2h_sdram2_clk
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);
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wire [29 - 1 : 0] intermediate;
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assign intermediate[0:0] = ~intermediate[1:1];
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assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
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assign intermediate[2:2] = intermediate[9:9];
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assign intermediate[3:3] = intermediate[9:9];
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assign intermediate[5:5] = intermediate[9:9];
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assign intermediate[6:6] = intermediate[9:9];
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assign intermediate[10:10] = intermediate[9:9];
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assign intermediate[11:11] = ~intermediate[12:12];
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assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
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assign intermediate[13:13] = intermediate[18:18];
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assign intermediate[15:15] = intermediate[18:18];
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assign intermediate[19:19] = intermediate[18:18];
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assign intermediate[20:20] = ~intermediate[21:21];
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assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
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assign intermediate[22:22] = intermediate[27:27];
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assign intermediate[24:24] = intermediate[27:27];
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assign intermediate[28:28] = intermediate[27:27];
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assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
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assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
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assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
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assign intermediate[4:4] = f2h_sdram0_READ[0:0];
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assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
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assign intermediate[9:9] = f2h_sdram0_clk[0:0];
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assign intermediate[14:14] = f2h_sdram1_READ[0:0];
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assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
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assign intermediate[18:18] = f2h_sdram1_clk[0:0];
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assign intermediate[23:23] = f2h_sdram2_READ[0:0];
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assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
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assign intermediate[27:27] = f2h_sdram2_clk[0:0];
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cyclonev_hps_interface_clocks_resets clocks_resets(
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.f2h_warm_rst_req_n({
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f2h_warm_rst_req_n[0:0] // 0:0
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})
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,.f2h_pending_rst_ack({
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1'b1 // 0:0
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})
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,.f2h_dbg_rst_req_n({
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1'b1 // 0:0
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})
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,.h2f_rst_n({
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h2f_rst_n[0:0] // 0:0
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})
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,.f2h_cold_rst_req_n({
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f2h_cold_rst_req_n[0:0] // 0:0
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})
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,.h2f_user0_clk({
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h2f_user0_clk[0:0] // 0:0
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})
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);
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cyclonev_hps_interface_dbg_apb debug_apb(
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.DBG_APB_DISABLE({
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1'b0 // 0:0
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})
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,.P_CLK_EN({
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1'b0 // 0:0
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})
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);
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cyclonev_hps_interface_tpiu_trace tpiu(
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.traceclk_ctl({
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1'b1 // 0:0
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})
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);
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cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
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.boot_from_fpga_ready({
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1'b0 // 0:0
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})
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,.boot_from_fpga_on_failure({
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1'b0 // 0:0
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})
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,.bsel_en({
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1'b0 // 0:0
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})
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,.csel_en({
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1'b0 // 0:0
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})
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,.csel({
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2'b01 // 1:0
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})
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,.bsel({
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3'b001 // 2:0
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})
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);
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cyclonev_hps_interface_fpga2hps fpga2hps(
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.port_size_config({
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2'b11 // 1:0
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})
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);
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cyclonev_hps_interface_hps2fpga hps2fpga(
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.port_size_config({
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2'b11 // 1:0
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})
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);
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cyclonev_hps_interface_fpga2sdram f2sdram(
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.cfg_rfifo_cport_map({
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16'b0010000100000000 // 15:0
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})
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,.cfg_wfifo_cport_map({
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16'b0010000100000000 // 15:0
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})
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,.rd_ready_3({
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1'b1 // 0:0
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})
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,.cmd_port_clk_2({
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intermediate[28:28] // 0:0
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})
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,.rd_ready_2({
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1'b1 // 0:0
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})
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,.cmd_port_clk_1({
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intermediate[19:19] // 0:0
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})
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,.rd_ready_1({
|
|
1'b1 // 0:0
|
|
})
|
|
,.cmd_port_clk_0({
|
|
intermediate[10:10] // 0:0
|
|
})
|
|
,.rd_ready_0({
|
|
1'b1 // 0:0
|
|
})
|
|
,.wrack_ready_2({
|
|
1'b1 // 0:0
|
|
})
|
|
,.wrack_ready_1({
|
|
1'b1 // 0:0
|
|
})
|
|
,.wrack_ready_0({
|
|
1'b1 // 0:0
|
|
})
|
|
,.cmd_ready_2({
|
|
intermediate[21:21] // 0:0
|
|
})
|
|
,.cmd_ready_1({
|
|
intermediate[12:12] // 0:0
|
|
})
|
|
,.cmd_ready_0({
|
|
intermediate[1:1] // 0:0
|
|
})
|
|
,.cfg_port_width({
|
|
12'b000000010110 // 11:0
|
|
})
|
|
,.rd_valid_3({
|
|
f2h_sdram2_READDATAVALID[0:0] // 0:0
|
|
})
|
|
,.rd_valid_2({
|
|
f2h_sdram1_READDATAVALID[0:0] // 0:0
|
|
})
|
|
,.rd_valid_1({
|
|
f2h_sdram0_READDATAVALID[0:0] // 0:0
|
|
})
|
|
,.rd_clk_3({
|
|
intermediate[22:22] // 0:0
|
|
})
|
|
,.rd_data_3({
|
|
f2h_sdram2_READDATA[63:0] // 63:0
|
|
})
|
|
,.rd_clk_2({
|
|
intermediate[13:13] // 0:0
|
|
})
|
|
,.rd_data_2({
|
|
f2h_sdram1_READDATA[63:0] // 63:0
|
|
})
|
|
,.rd_clk_1({
|
|
intermediate[3:3] // 0:0
|
|
})
|
|
,.rd_data_1({
|
|
f2h_sdram0_READDATA[127:64] // 63:0
|
|
})
|
|
,.rd_clk_0({
|
|
intermediate[2:2] // 0:0
|
|
})
|
|
,.rd_data_0({
|
|
f2h_sdram0_READDATA[63:0] // 63:0
|
|
})
|
|
,.cfg_axi_mm_select({
|
|
6'b000000 // 5:0
|
|
})
|
|
,.cmd_valid_2({
|
|
intermediate[26:26] // 0:0
|
|
})
|
|
,.cmd_valid_1({
|
|
intermediate[17:17] // 0:0
|
|
})
|
|
,.cmd_valid_0({
|
|
intermediate[8:8] // 0:0
|
|
})
|
|
,.cfg_cport_rfifo_map({
|
|
18'b000000000011010000 // 17:0
|
|
})
|
|
,.wr_data_3({
|
|
2'b00 // 89:88
|
|
,f2h_sdram2_BYTEENABLE[7:0] // 87:80
|
|
,16'b0000000000000000 // 79:64
|
|
,f2h_sdram2_WRITEDATA[63:0] // 63:0
|
|
})
|
|
,.wr_data_2({
|
|
2'b00 // 89:88
|
|
,f2h_sdram1_BYTEENABLE[7:0] // 87:80
|
|
,16'b0000000000000000 // 79:64
|
|
,f2h_sdram1_WRITEDATA[63:0] // 63:0
|
|
})
|
|
,.wr_data_1({
|
|
2'b00 // 89:88
|
|
,f2h_sdram0_BYTEENABLE[15:8] // 87:80
|
|
,16'b0000000000000000 // 79:64
|
|
,f2h_sdram0_WRITEDATA[127:64] // 63:0
|
|
})
|
|
,.cfg_cport_type({
|
|
12'b000000111111 // 11:0
|
|
})
|
|
,.wr_data_0({
|
|
2'b00 // 89:88
|
|
,f2h_sdram0_BYTEENABLE[7:0] // 87:80
|
|
,16'b0000000000000000 // 79:64
|
|
,f2h_sdram0_WRITEDATA[63:0] // 63:0
|
|
})
|
|
,.cfg_cport_wfifo_map({
|
|
18'b000000000011010000 // 17:0
|
|
})
|
|
,.wr_clk_3({
|
|
intermediate[24:24] // 0:0
|
|
})
|
|
,.wr_clk_2({
|
|
intermediate[15:15] // 0:0
|
|
})
|
|
,.wr_clk_1({
|
|
intermediate[6:6] // 0:0
|
|
})
|
|
,.wr_clk_0({
|
|
intermediate[5:5] // 0:0
|
|
})
|
|
,.cmd_data_2({
|
|
18'b000000000000000000 // 59:42
|
|
,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
|
|
,3'b000 // 33:31
|
|
,f2h_sdram2_ADDRESS[28:0] // 30:2
|
|
,intermediate[25:25] // 1:1
|
|
,intermediate[23:23] // 0:0
|
|
})
|
|
,.cmd_data_1({
|
|
18'b000000000000000000 // 59:42
|
|
,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
|
|
,3'b000 // 33:31
|
|
,f2h_sdram1_ADDRESS[28:0] // 30:2
|
|
,intermediate[16:16] // 1:1
|
|
,intermediate[14:14] // 0:0
|
|
})
|
|
,.cmd_data_0({
|
|
18'b000000000000000000 // 59:42
|
|
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
|
|
,4'b0000 // 33:30
|
|
,f2h_sdram0_ADDRESS[27:0] // 29:2
|
|
,intermediate[7:7] // 1:1
|
|
,intermediate[4:4] // 0:0
|
|
})
|
|
);
|
|
|
|
endmodule
|