74 lines
2.0 KiB
Systemverilog
74 lines
2.0 KiB
Systemverilog
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module vga_out
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(
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input clk,
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input ypbpr_en,
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input hsync,
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input vsync,
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input csync,
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input de,
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input [23:0] din,
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output [23:0] dout,
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output reg hsync_o,
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output reg vsync_o,
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output reg csync_o,
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output reg de_o
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);
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wire [7:0] red = din[23:16];
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wire [7:0] green = din[15:8];
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wire [7:0] blue = din[7:0];
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// http://marsee101.blog19.fc2.com/blog-entry-2311.html
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// Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B)
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// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B)
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// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B)
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reg [7:0] y, pb, pr;
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reg [23:0] rgb;
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always @(posedge clk) begin
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reg [18:0] y_1r, pb_1r, pr_1r;
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reg [18:0] y_1g, pb_1g, pr_1g;
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reg [18:0] y_1b, pb_1b, pr_1b;
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reg [18:0] y_2, pb_2, pr_2;
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reg [23:0] din1, din2;
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reg hsync2, vsync2, csync2, de2;
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reg hsync1, vsync1, csync1, de1;
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y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
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pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
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pr_1r <= 19'd32768 + {red, 7'd0};
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y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0};
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pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green;
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pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0};
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y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue;
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pb_1b <= {blue, 7'd0};
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pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue;
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y_2 <= y_1r + y_1g + y_1b;
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pb_2 <= pb_1r - pb_1g + pb_1b;
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pr_2 <= pr_1r - pr_1g - pr_1b;
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y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8];
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pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8];
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pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8];
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hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
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vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
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csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
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de_o <= de2; de2 <= de1; de1 <= de;
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rgb <= din2; din2 <= din1; din1 <= din;
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end
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assign dout = ypbpr_en ? {pr, y, pb} : rgb;
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endmodule
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