100 lines
1.7 KiB
Systemverilog
100 lines
1.7 KiB
Systemverilog
//
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//
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// Copyright (c) 2018 Sorgelig
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//
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// This program is GPL Licensed. See COPYING for the full license.
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//
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//
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module video_cleaner
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(
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input clk_vid,
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input ce_pix,
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input [7:0] R,
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input [7:0] G,
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input [7:0] B,
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input HSync,
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input VSync,
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input HBlank,
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input VBlank,
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//optional de
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input DE_in,
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// video output signals
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output reg [7:0] VGA_R,
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output reg [7:0] VGA_G,
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output reg [7:0] VGA_B,
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output reg VGA_VS,
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output reg VGA_HS,
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output VGA_DE,
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// optional aligned blank
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output reg HBlank_out,
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output reg VBlank_out,
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// optional aligned de
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output reg DE_out
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);
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wire hs, vs;
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s_fix sync_v(clk_vid, HSync, hs);
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s_fix sync_h(clk_vid, VSync, vs);
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wire hbl = hs | HBlank;
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wire vbl = vs | VBlank;
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assign VGA_DE = ~(HBlank_out | VBlank_out);
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always @(posedge clk_vid) begin
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if(ce_pix) begin
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HBlank_out <= hbl;
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VGA_HS <= hs;
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if(~VGA_HS & hs) VGA_VS <= vs;
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VGA_R <= R;
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VGA_G <= G;
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VGA_B <= B;
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DE_out <= DE_in;
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if(HBlank_out & ~hbl) VBlank_out <= vbl;
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end
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end
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endmodule
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module s_fix
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(
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input clk,
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input sync_in,
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output sync_out
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);
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assign sync_out = sync_in ^ pol;
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reg pol;
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always @(posedge clk) begin
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integer pos = 0, neg = 0, cnt = 0;
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reg s1,s2;
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s1 <= sync_in;
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s2 <= s1;
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if(~s2 & s1) neg <= cnt;
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if(s2 & ~s1) pos <= cnt;
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cnt <= cnt + 1;
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if(s2 != s1) cnt <= 0;
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pol <= pos > neg;
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end
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endmodule
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