38 lines
1.6 KiB
Tcl
38 lines
1.6 KiB
Tcl
# Specify root clocks
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
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create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
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create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
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derive_pll_clocks
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create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
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-name HDMI_CLK [get_ports HDMI_TX_CLK]
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derive_clock_uncertainty
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# Decouple different clock groups (to simplify routing)
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set_clock_groups -exclusive \
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-group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
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-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
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-group [get_clocks { *|h2f_user0_clk}] \
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-group [get_clocks { FPGA_CLK1_50 }] \
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-group [get_clocks { FPGA_CLK2_50 }] \
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-group [get_clocks { FPGA_CLK3_50 }]
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set_output_delay -max -clock HDMI_CLK 4.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
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set_output_delay -min -clock HDMI_CLK 3.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
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set_false_path -from [get_ports {KEY*}]
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set_false_path -from [get_ports {BTN_*}]
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set_false_path -to [get_ports {LED_*}]
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set_false_path -to [get_ports {VGA_*}]
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set_false_path -to [get_ports {AUDIO_SPDIF}]
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set_false_path -to [get_ports {AUDIO_L}]
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set_false_path -to [get_ports {AUDIO_R}]
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set_false_path -to {cfg[*]}
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set_false_path -from {cfg[*]}
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set_false_path -to {wcalc[*] hcalc[*]}
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