158 lines
2.1 KiB
Verilog
158 lines
2.1 KiB
Verilog
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module audio_out
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#(
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parameter CLK_RATE = 50000000
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)
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(
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input reset,
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input clk,
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//0 - 48KHz, 1 - 96KHz
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input sample_rate,
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input [15:0] left_in,
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input [15:0] right_in,
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// I2S
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output i2s_bclk,
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output i2s_lrclk,
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output i2s_data,
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// SPDIF
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output spdif,
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// Sigma-Delta DAC
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output dac_l,
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output dac_r
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);
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localparam AUDIO_RATE = 48000;
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localparam AUDIO_DW = 16;
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localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
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localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;
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wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];
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reg mclk_ce;
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always @(posedge clk) begin
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reg [31:0] cnt;
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mclk_ce <= 0;
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cnt = cnt + real_ce;
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if(cnt >= CLK_RATE) begin
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cnt = cnt - CLK_RATE;
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mclk_ce <= 1;
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end
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end
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reg i2s_ce;
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always @(posedge clk) begin
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reg div;
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i2s_ce <= 0;
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if(mclk_ce) begin
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div <= ~div;
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i2s_ce <= div;
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end
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end
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reg lpf_ce;
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always @(posedge clk) begin
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integer div;
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lpf_ce <= 0;
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if(mclk_ce) begin
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div <= div + 1;
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if(div == FILTER_DIV) begin
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div <= 0;
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lpf_ce <= 1;
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end
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end
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end
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i2s i2s
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(
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.reset(reset),
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.clk(clk),
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.ce(i2s_ce),
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.sclk(i2s_bclk),
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.lrclk(i2s_lrclk),
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.sdata(i2s_data),
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.left_chan(al),
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.right_chan(ar)
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);
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spdif toslink
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(
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.rst_i(reset),
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.clk_i(clk),
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.bit_out_en_i(mclk_ce),
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.sample_i({ar,al}),
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.spdif_o(spdif)
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);
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sigma_delta_dac #(15) sd_l
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(
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.CLK(clk),
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.RESET(reset),
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.DACin({~al[15], al[14:0]}),
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.DACout(dac_l)
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);
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sigma_delta_dac #(15) sd_r
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(
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.CLK(clk),
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.RESET(reset),
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.DACin({~ar[15], ar[14:0]}),
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.DACout(dac_r)
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);
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wire [15:0] al, ar;
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lpf_aud lpf_l
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(
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.CLK(clk),
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.CE(lpf_ce),
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.IDATA(left_in),
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.ODATA(al)
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);
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lpf_aud lpf_r
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(
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.CLK(clk),
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.CE(lpf_ce),
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.IDATA(right_in),
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.ODATA(ar)
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);
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endmodule
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module lpf_aud
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(
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input CLK,
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input CE,
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input [15:0] IDATA,
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output reg [15:0] ODATA
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);
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reg [511:0] acc;
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reg [20:0] sum;
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always @(*) begin
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integer i;
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sum = 0;
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for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
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end
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always @(posedge CLK) begin
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if(CE) begin
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acc <= {acc[495:0], IDATA};
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ODATA <= sum[20:5];
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end
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end
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endmodule
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