53 lines
965 B
Verilog
53 lines
965 B
Verilog
module scanlines #(parameter v2=0)
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(
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input clk,
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input [1:0] scanlines,
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input [23:0] din,
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output reg [23:0] dout,
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input hs,vs
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);
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reg [1:0] scanline;
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always @(posedge clk) begin
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reg old_hs, old_vs;
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old_hs <= hs;
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old_vs <= vs;
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if(old_hs && ~hs) begin
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if(v2) begin
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scanline <= scanline + 1'd1;
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if (scanline == scanlines) scanline <= 0;
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end
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else scanline <= scanline ^ scanlines;
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end
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if(old_vs && ~vs) scanline <= 0;
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end
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wire [7:0] r,g,b;
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assign {r,g,b} = din;
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always @(*) begin
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case(scanline)
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1: // reduce 25% = 1/2 + 1/4
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dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
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{1'b0, g[7:1]} + {2'b00, g[7:2]},
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{1'b0, b[7:1]} + {2'b00, b[7:2]}};
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2: // reduce 50% = 1/2
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dout = {{1'b0, r[7:1]},
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{1'b0, g[7:1]},
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{1'b0, b[7:1]}};
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3: // reduce 75% = 1/4
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dout = {{2'b00, r[7:2]},
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{2'b00, g[7:2]},
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{2'b00, b[7:2]}};
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default: dout = {r,g,b};
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endcase
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end
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endmodule
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