538 lines
14 KiB
Systemverilog
538 lines
14 KiB
Systemverilog
//
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// sd_card.v
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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// Copyright (c) 2015-2018 Sorgelig
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the Lesser GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// http://elm-chan.org/docs/mmc/mmc_e.html
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//
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/////////////////////////////////////////////////////////////////////////
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//
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// Made module syncrhronous. Total code refactoring. (Sorgelig)
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// clk_spi must be at least 4 x sck for proper work.
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module sd_card #(parameter WIDE = 0)
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(
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input clk_sys,
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input reset,
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input sdhc,
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output [31:0] sd_lba,
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output reg sd_rd,
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output reg sd_wr,
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input sd_ack,
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input sd_ack_conf,
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input [AW:0] sd_buff_addr,
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input [DW:0] sd_buff_dout,
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output [DW:0] sd_buff_din,
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input sd_buff_wr,
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// SPI interface
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input clk_spi,
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input ss,
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input sck,
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input mosi,
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output reg miso
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);
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localparam AW = WIDE ? 7 : 8;
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localparam DW = WIDE ? 15 : 7;
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assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]};
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wire[31:0] OCR = { 1'b1, sdhc, 30'd0 }; // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished
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wire [7:0] READ_DATA_TOKEN = 8'hfe;
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wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
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// number of bytes to wait after a command before sending the reply
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localparam NCR=3;
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localparam RD_STATE_IDLE = 0;
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localparam RD_STATE_WAIT_IO = 1;
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localparam RD_STATE_SEND_TOKEN = 2;
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localparam RD_STATE_SEND_DATA = 3;
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localparam RD_STATE_WAIT_M = 4;
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localparam WR_STATE_IDLE = 0;
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localparam WR_STATE_EXP_DTOKEN = 1;
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localparam WR_STATE_RECV_DATA = 2;
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localparam WR_STATE_RECV_CRC0 = 3;
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localparam WR_STATE_RECV_CRC1 = 4;
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localparam WR_STATE_SEND_DRESP = 5;
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localparam WR_STATE_BUSY = 6;
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sdbuf #(WIDE) buffer
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(
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.clock_a(clk_sys),
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.address_a(sd_buff_addr),
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.data_a(sd_buff_dout),
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.wren_a(sd_ack & sd_buff_wr),
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.q_a(sd_buff_din),
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.clock_b(clk_spi),
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.address_b(buffer_ptr),
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.data_b(buffer_din),
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.wren_b(buffer_wr),
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.q_b(buffer_dout)
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);
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sdbuf #(WIDE) conf
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(
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.clock_a(clk_sys),
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.address_a(sd_buff_addr),
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.data_a(sd_buff_dout),
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.wren_a(sd_ack_conf & sd_buff_wr),
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.clock_b(clk_spi),
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.address_b(buffer_ptr),
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.q_b(config_dout)
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);
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reg [31:0] lba, new_lba;
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reg [8:0] buffer_ptr;
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reg [7:0] buffer_din;
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wire [7:0] buffer_dout;
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wire [7:0] config_dout;
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reg buffer_wr;
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always @(posedge clk_spi) begin
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reg [2:0] read_state;
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reg [2:0] write_state;
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reg [6:0] sbuf;
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reg cmd55;
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reg [7:0] cmd;
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reg [2:0] bit_cnt;
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reg [3:0] byte_cnt;
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reg [7:0] reply;
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reg [7:0] reply0, reply1, reply2, reply3;
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reg [3:0] reply_len;
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reg tx_finish;
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reg rx_finish;
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reg old_sck;
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reg synced;
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reg [5:0] ack;
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reg io_ack;
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reg [4:0] idle_cnt = 0;
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reg [2:0] wait_m_cnt;
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if(buffer_wr & ~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1;
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buffer_wr <= 0;
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ack <= {ack[4:0], sd_ack};
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if(ack[5:4] == 2'b10) io_ack <= 1;
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if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0;
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old_sck <= sck;
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if(~ss) idle_cnt <= 31;
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else if(~old_sck && sck && idle_cnt) idle_cnt <= idle_cnt - 1'd1;
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if(reset || !idle_cnt) begin
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bit_cnt <= 0;
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byte_cnt <= 15;
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synced <= 0;
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miso <= 1;
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sbuf <= 7'b1111111;
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tx_finish <= 0;
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rx_finish <= 0;
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read_state <= RD_STATE_IDLE;
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write_state <= WR_STATE_IDLE;
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end
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if(old_sck & ~sck & ~ss) begin
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tx_finish <= 0;
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miso <= 1; // default: send 1's (busy/wait)
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if(byte_cnt == 5+NCR) begin
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miso <= reply[~bit_cnt];
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if(bit_cnt == 7) begin
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// these three commands all have a reply_len of 0 and will thus
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// not send more than a single reply byte
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// CMD9: SEND_CSD
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// CMD10: SEND_CID
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if((cmd == 'h49) | (cmd == 'h4a))
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read_state <= RD_STATE_SEND_TOKEN; // jump directly to data transmission
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// CMD17/CMD18
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if((cmd == 'h51) | (cmd == 'h52)) begin
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io_ack <= 0;
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read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller
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lba <= new_lba;
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sd_rd <= 1; // trigger request to io controller
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end
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end
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end
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else if((reply_len > 0) && (byte_cnt == 5+NCR+1)) miso <= reply0[~bit_cnt];
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else if((reply_len > 1) && (byte_cnt == 5+NCR+2)) miso <= reply1[~bit_cnt];
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else if((reply_len > 2) && (byte_cnt == 5+NCR+3)) miso <= reply2[~bit_cnt];
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else if((reply_len > 3) && (byte_cnt == 5+NCR+4)) miso <= reply3[~bit_cnt];
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else begin
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if(byte_cnt > 5+NCR && read_state==RD_STATE_IDLE && write_state==WR_STATE_IDLE) tx_finish <= 1;
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end
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// ---------- read state machine processing -------------
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case(read_state)
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RD_STATE_IDLE: ; // do nothing
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// waiting for io controller to return data
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RD_STATE_WAIT_IO: begin
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if(io_ack & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN;
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end
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// send data token
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RD_STATE_SEND_TOKEN: begin
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miso <= READ_DATA_TOKEN[~bit_cnt];
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if(bit_cnt == 7) begin
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read_state <= RD_STATE_SEND_DATA; // next: send data
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buffer_ptr <= 0;
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if(cmd == 'h49) buffer_ptr <= 16;
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end
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end
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// send data
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RD_STATE_SEND_DATA: begin
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miso <= ((cmd == 'h49) | (cmd == 'h4A)) ? config_dout[~bit_cnt] : buffer_dout[~bit_cnt];
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if(bit_cnt == 7) begin
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// sent 512 sector data bytes?
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if((cmd == 'h51) & &buffer_ptr) read_state <= RD_STATE_IDLE;
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else if((cmd == 'h52) & &buffer_ptr) begin
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read_state <= RD_STATE_WAIT_M;
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wait_m_cnt <= 0;
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end
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// sent 16 cid/csd data bytes?
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else if(((cmd == 'h49) | (cmd == 'h4a)) & (&buffer_ptr[3:0])) read_state <= RD_STATE_IDLE;
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// not done yet -> trigger read of next data byte
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else buffer_ptr <= buffer_ptr + 1'd1;
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end
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end
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RD_STATE_WAIT_M: begin
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if(bit_cnt == 7) begin
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wait_m_cnt <= wait_m_cnt + 1'd1;
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if(&wait_m_cnt) begin
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lba <= lba + 1;
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io_ack <= 0;
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sd_rd <= 1;
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read_state <= RD_STATE_WAIT_IO;
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end
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end
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end
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endcase
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// ------------------ write support ----------------------
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// send write data response
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if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt];
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// busy after write until the io controller sends ack
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if(write_state == WR_STATE_BUSY) miso <= 0;
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end
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if(~old_sck & sck & ~ss) begin
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if(synced) bit_cnt <= bit_cnt + 1'd1;
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// assemble byte
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if(bit_cnt != 7) begin
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sbuf[6:0] <= { sbuf[5:0], mosi };
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// resync while waiting for token
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if(write_state==WR_STATE_EXP_DTOKEN) begin
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if(cmd == 'h58) begin
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if({sbuf,mosi} == 8'hfe) begin
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write_state <= WR_STATE_RECV_DATA;
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buffer_ptr <= 0;
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bit_cnt <= 0;
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end
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end
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else begin
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if({sbuf,mosi} == 8'hfc) begin
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write_state <= WR_STATE_RECV_DATA;
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buffer_ptr <= 0;
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bit_cnt <= 0;
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end
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if({sbuf,mosi} == 8'hfd) begin
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write_state <= WR_STATE_IDLE;
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rx_finish <= 1;
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bit_cnt <= 0;
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end
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end
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end
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end
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else begin
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// finished reading one byte
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// byte counter runs against 15 byte boundary
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if(byte_cnt != 15) byte_cnt <= byte_cnt + 1'd1;
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// byte_cnt > 6 -> complete command received
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// first byte of valid command is 01xxxxxx
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// don't accept new commands once a write or read command has been accepted
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if((byte_cnt > 5) & (write_state == WR_STATE_IDLE) & (read_state == RD_STATE_IDLE) && !rx_finish) begin
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byte_cnt <= 0;
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cmd <= { sbuf, mosi};
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// set cmd55 flag if previous command was 55
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cmd55 <= (cmd == 'h77);
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end
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if((byte_cnt > 5) & (read_state == RD_STATE_WAIT_M) && ({sbuf, mosi} == 8'h4c)) begin
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byte_cnt <= 0;
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rx_finish <= 0;
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cmd <= {sbuf, mosi};
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read_state <= RD_STATE_IDLE;
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end
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// parse additional command bytes
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if(byte_cnt == 0) new_lba[31:24] <= { sbuf, mosi};
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if(byte_cnt == 1) new_lba[23:16] <= { sbuf, mosi};
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if(byte_cnt == 2) new_lba[15:8] <= { sbuf, mosi};
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if(byte_cnt == 3) new_lba[7:0] <= { sbuf, mosi};
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// last byte (crc) received, evaluate
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if(byte_cnt == 4) begin
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// default:
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reply <= 4; // illegal command
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reply_len <= 0; // no extra reply bytes
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rx_finish <= 1;
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case(cmd)
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// CMD0: GO_IDLE_STATE
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'h40: reply <= 1; // ok, busy
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// CMD1: SEND_OP_COND
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'h41: reply <= 0; // ok, not busy
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// CMD8: SEND_IF_COND (V2 only)
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'h48: begin
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reply <= 1; // ok, busy
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reply0 <= 'h00;
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reply1 <= 'h00;
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reply2 <= 'h01;
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reply3 <= 'hAA;
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reply_len <= 4;
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end
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// CMD9: SEND_CSD
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'h49: reply <= 0; // ok
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// CMD10: SEND_CID
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'h4a: reply <= 0; // ok
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// CMD12: STOP_TRANSMISSION
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'h4c: reply <= 0; // ok
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// CMD13: SEND_STATUS
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'h4d: begin
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reply <= 'h00; // ok
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reply0 <='h00;
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reply_len <= 1;
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end
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// CMD16: SET_BLOCKLEN
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'h50: begin
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// we only support a block size of 512
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if(new_lba == 512) reply <= 0; // ok
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else reply <= 'h40; // parmeter error
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end
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// CMD17: READ_SINGLE_BLOCK
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'h51: reply <= 0; // ok
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// CMD18: READ_MULTIPLE
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'h52: reply <= 0; // ok
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// ACMD23: SET_WR_BLK_ERASE_COUNT
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'h57: reply <= 0; //ok
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// CMD24: WRITE_BLOCK
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'h58,
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// CMD25: WRITE_MULTIPLE
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'h59: begin
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reply <= 0; // ok
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write_state <= WR_STATE_EXP_DTOKEN; // expect data token
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rx_finish <=0;
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lba <= new_lba;
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end
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// ACMD41: APP_SEND_OP_COND
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'h69: if(cmd55) reply <= 0; // ok, not busy
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// CMD55: APP_COND
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'h77: reply <= 1; // ok, busy
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// CMD58: READ_OCR
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'h7a: begin
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reply <= 0; // ok
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reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card
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reply1 <= OCR[23:16];
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reply2 <= OCR[15:8];
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reply3 <= OCR[7:0];
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reply_len <= 4;
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end
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// CMD59: CRC_ON_OFF
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'h7b: reply <= 0; // ok
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endcase
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end
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// ---------- handle write -----------
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case(write_state)
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// do nothing in idle state
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WR_STATE_IDLE: ;
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// waiting for data token
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WR_STATE_EXP_DTOKEN: begin
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buffer_ptr <= 0;
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if(cmd == 'h58) begin
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if({sbuf,mosi} == 8'hfe) write_state <= WR_STATE_RECV_DATA;
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end
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else begin
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if({sbuf,mosi} == 8'hfc) write_state <= WR_STATE_RECV_DATA;
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if({sbuf,mosi} == 8'hfd) begin
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write_state <= WR_STATE_IDLE;
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rx_finish <= 1;
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end
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end
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end
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// transfer 512 bytes
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WR_STATE_RECV_DATA: begin
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// push one byte into local buffer
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buffer_wr <= 1;
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buffer_din <= {sbuf, mosi};
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// all bytes written?
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if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0;
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end
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// transfer 1st crc byte
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WR_STATE_RECV_CRC0:
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write_state <= WR_STATE_RECV_CRC1;
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// transfer 2nd crc byte
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WR_STATE_RECV_CRC1:
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write_state <= WR_STATE_SEND_DRESP;
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// send data response
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WR_STATE_SEND_DRESP: begin
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write_state <= WR_STATE_BUSY;
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io_ack <= 0;
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sd_wr <= 1;
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end
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// wait for io controller to accept data
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WR_STATE_BUSY:
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if(io_ack) begin
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if(cmd == 'h59) begin
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write_state <= WR_STATE_EXP_DTOKEN;
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lba <= lba + 1;
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end
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else begin
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write_state <= WR_STATE_IDLE;
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rx_finish <= 1;
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end
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end
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endcase
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end
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// wait for first 0 bit until start counting bits
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if(!synced && !mosi) begin
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synced <= 1;
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bit_cnt <= 1; // byte assembly prepare for next time loop
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sbuf <= 7'b1111110; // byte assembly prepare for next time loop
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rx_finish<= 0;
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end else if (synced && tx_finish && rx_finish ) begin
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synced <= 0;
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bit_cnt <= 0;
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rx_finish<= 0;
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end
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end
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end
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endmodule
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module sdbuf #(parameter WIDE)
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(
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input clock_a,
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input [AW:0] address_a,
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input [DW:0] data_a,
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input wren_a,
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output reg [DW:0] q_a,
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input clock_b,
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input [8:0] address_b,
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input [7:0] data_b,
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input wren_b,
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output reg [7:0] q_b
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);
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localparam AW = WIDE ? 7 : 8;
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localparam DW = WIDE ? 15 : 7;
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always@(posedge clock_a) begin
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if(wren_a) begin
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ram[address_a] <= data_a;
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q_a <= data_a;
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end
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else begin
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q_a <= ram[address_a];
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end
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end
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generate
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if(WIDE) begin
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reg [1:0][7:0] ram[1<<8];
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always@(posedge clock_b) begin
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if(wren_b) begin
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ram[address_b[8:1]][address_b[0]] <= data_b;
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q_b <= data_b;
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end
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else begin
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q_b <= ram[address_b[8:1]][address_b[0]];
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end
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end
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end
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else begin
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reg [7:0] ram[1<<9];
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always@(posedge clock_b) begin
|
|
if(wren_b) begin
|
|
ram[address_b] <= data_b;
|
|
q_b <= data_b;
|
|
end
|
|
else begin
|
|
q_b <= ram[address_b];
|
|
end
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|