52 lines
1.7 KiB
Systemverilog
52 lines
1.7 KiB
Systemverilog
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module vga_out
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(
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input clk,
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input ypbpr_en,
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input hsync,
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input vsync,
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input csync,
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input [23:0] din,
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output [23:0] dout,
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output reg hsync_o,
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output reg vsync_o,
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output reg csync_o
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);
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wire [5:0] red = din[23:18];
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wire [5:0] green = din[15:10];
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wire [5:0] blue = din[7:2];
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// http://marsee101.blog19.fc2.com/blog-entry-2311.html
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// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
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// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
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// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
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reg [18:0] y_2, pb_2, pr_2;
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reg [7:0] y, pb, pr;
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reg [23:0] din2, din3;
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reg hsync2, vsync2, csync2;
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always @(posedge clk) begin
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y_2 <= 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
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pb_2 <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
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pr_2 <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
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y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8];
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pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8];
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pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8];
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hsync_o <= hsync2; hsync2 <= hsync;
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vsync_o <= vsync2; vsync2 <= vsync;
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csync_o <= csync2; csync2 <= csync;
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din2 <= din;
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din3 <= din2;
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end
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assign dout = ypbpr_en ? {pr, y, pb} : din3;
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endmodule
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