31 lines
2.8 KiB
Plaintext
31 lines
2.8 KiB
Plaintext
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
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set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll/pll_0002.v ]
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll/pll_0002.qip ]
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_q13.qip ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_top.v ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
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set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
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set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
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