361 lines
11 KiB
Verilog
361 lines
11 KiB
Verilog
/* verilator lint_off UNUSED */
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/* verilator lint_off SYNCASYNCNET */
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// scsi.v
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// implements a target only scsi device
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module scsi
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(
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input clk,
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// scsi interface
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input rst, // bus reset from initiator
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input sel,
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input atn, // initiator requests to send a message
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output bsy, // target holds bus
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output msg,
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output cd,
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output io,
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output req,
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input ack, // initiator acknowledges a request
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input [7:0] din, // data from initiator to target
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output [7:0] dout, // data from target to initiator
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// interface to io controller
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input img_mounted,
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input [23:0] img_blocks,
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output [31:0] io_lba,
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output reg io_rd,
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output reg io_wr,
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input io_ack,
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input [7:0] sd_buff_addr,
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input [15:0] sd_buff_dout,
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output reg [15:0] sd_buff_din,
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input sd_buff_wr
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);
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// SCSI device id
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parameter [7:0] ID = 0;
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`define PHASE_IDLE 3'd0
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`define PHASE_CMD_IN 3'd1
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`define PHASE_DATA_OUT 3'd2
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`define PHASE_DATA_IN 3'd3
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`define PHASE_STATUS_OUT 3'd4
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`define PHASE_MESSAGE_OUT 3'd5
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reg [2:0] phase;
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// ---------------- buffer read engine -----------------------
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// the buffer itself. Can hold one sector
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reg [7:0] buffer_out0 [256];
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always @(posedge clk) sd_buff_din[7:0] <= buffer_out0[sd_buff_addr];
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reg [7:0] buffer_out1 [256];
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always @(posedge clk) sd_buff_din[15:8] <= buffer_out1[sd_buff_addr];
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// ---------------- buffer write engine ----------------------
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// the buffer itself. Can hold one sector
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reg [7:0] buffer_in0 [256];
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always @(posedge clk) if(sd_buff_wr & io_ack) buffer_in0[sd_buff_addr] <= sd_buff_dout[7:0];
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reg [7:0] buffer_in1 [256];
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always @(posedge clk) if(sd_buff_wr & io_ack) buffer_in1[sd_buff_addr] <= sd_buff_dout[15:8];
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// -----------------------------------------------------------
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// status replies
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reg [7:0] status;
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`define STATUS_OK 8'h00
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`define STATUS_CHECK_CONDITION 8'h02
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// message codes
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`define MSG_CMD_COMPLETE 8'h00
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// drive scsi signals according to phase
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assign msg = (phase == `PHASE_MESSAGE_OUT);
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assign cd = (phase == `PHASE_CMD_IN) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
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assign io = (phase == `PHASE_DATA_OUT) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
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assign req = (phase != `PHASE_IDLE) && !ack && !io_rd && !io_wr && !io_ack;
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assign bsy = (phase != `PHASE_IDLE);
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assign dout = (phase == `PHASE_STATUS_OUT)?status:
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(phase == `PHASE_MESSAGE_OUT)?`MSG_CMD_COMPLETE:
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(phase == `PHASE_DATA_OUT)?cmd_dout:
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8'h00;
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// de-multiplex different data sources
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wire [7:0] cmd_dout =
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cmd_read?buffer_dout:
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cmd_inquiry?inquiry_dout:
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cmd_read_capacity?read_capacity_dout:
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cmd_mode_sense?mode_sense_dout:
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8'h00;
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// output of inquiry command, identify as "SEAGATE ST225N"
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wire [7:0] inquiry_dout =
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(data_cnt == 32'd4 )?8'd32: // length
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(data_cnt == 32'd8 )?" ":(data_cnt == 32'd9 )?"S":
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(data_cnt == 32'd10)?"E":(data_cnt == 32'd11)?"A":
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(data_cnt == 32'd12)?"G":(data_cnt == 32'd13)?"A":
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(data_cnt == 32'd14)?"T":(data_cnt == 32'd15)?"E":
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(data_cnt == 32'd16)?" ":(data_cnt == 32'd17)?" ":
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(data_cnt == 32'd18)?" ":(data_cnt == 32'd19)?" ":
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(data_cnt == 32'd20)?" ":(data_cnt == 32'd21)?" ":
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(data_cnt == 32'd22)?" ":(data_cnt == 32'd23)?" ":
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(data_cnt == 32'd24)?" ":(data_cnt == 32'd25)?" ":
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(data_cnt == 32'd26)?"S":(data_cnt == 32'd27)?"T":
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(data_cnt == 32'd28)?"2":(data_cnt == 32'd29)?"2":
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(data_cnt == 32'd30)?"5":(data_cnt == 32'd31)?"N" + ID: // TESTING. ElectronAsh.
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8'h00;
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// output of read capacity command
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//wire [31:0] capacity = 32'd41056; // 40960 + 96 blocks = 20MB
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//wire [31:0] capacity = 32'd1024096; // 1024000 + 96 blocks = 500MB
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reg [31:0] capacity;
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always @(posedge clk) begin
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if (img_mounted) capacity <= img_blocks + 8'd96;
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end
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wire [31:0] capacity_m1 = capacity - 32'd1;
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wire [7:0] read_capacity_dout =
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(data_cnt == 32'd0 )?capacity_m1[31:24]:
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(data_cnt == 32'd1 )?capacity_m1[23:16]:
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(data_cnt == 32'd2 )?capacity_m1[15:8]:
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(data_cnt == 32'd3 )?capacity_m1[7:0]:
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(data_cnt == 32'd6 )?8'd2: // 512 bytes per sector
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8'h00;
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wire [7:0] mode_sense_dout =
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(data_cnt == 32'd3 )?8'd8:
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(data_cnt == 32'd5 )?capacity[23:16]:
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(data_cnt == 32'd6 )?capacity[15:8]:
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(data_cnt == 32'd7 )?capacity[7:0]:
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(data_cnt == 32'd10 )?8'd2:
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8'h00;
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// clock data out of buffer to allow for embedded ram
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reg [7:0] buffer_dout;
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always @(posedge clk) buffer_dout <= data_cnt[0] ? buffer_in1[data_cnt[8:1]] : buffer_in0[data_cnt[8:1]];
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// buffer to store incoming commands
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reg [3:0] cmd_cnt;
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reg [7:0] cmd [9:0];
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/* ----------------------- request data from/to io controller ----------------------- */
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// base address of current block. Subtract one when writing since the writing happens
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// after a block has been transferred and data_cnt has thus already been increased by 512
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assign io_lba = lba + { 9'd0, data_cnt[31:9] } -
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(cmd_write ? 32'd1 : 32'd0);
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wire req_rd = ((phase == `PHASE_DATA_OUT) && cmd_read && (data_cnt[8:0] == 0) && !data_complete);
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wire req_wr = ((((phase == `PHASE_DATA_IN) && (data_cnt[8:0] == 0) && (data_cnt != 0)) || (phase == `PHASE_STATUS_OUT)) && cmd_write);
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always @(posedge clk) begin
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reg old_rd, old_wr;
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old_rd <= req_rd;
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old_wr <= req_wr;
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if(io_ack) begin
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io_rd <= 1'b0;
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io_wr <= 1'b0;
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end else begin
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// generate an io_rd signal whenever the first byte of a 512 byte block is required and io_wr whenever
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// the last byte of a 512 byte block has been revceived
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if(~old_rd & req_rd) io_rd <= 1;
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// generate an io_wr signal whenever a 512 byte block has been received or when the status
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// phase of a write command has been reached
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if(~old_wr & req_wr) io_wr <= 1;
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end
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end
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reg stb_ack;
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reg stb_adv;
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always @(posedge clk) begin
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reg old_ack;
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old_ack <= ack;
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stb_ack <= (~old_ack & ack); // on rising edge
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stb_adv <= (old_ack & ~ack); // on falling edge
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end
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// store data on rising edge of ack, ...
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always @(posedge clk) begin
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if(stb_ack) begin
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if(phase == `PHASE_CMD_IN) cmd[cmd_cnt] <= din;
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if(phase == `PHASE_DATA_IN) begin
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if(data_cnt[0]) buffer_out1[data_cnt[8:1]] <= din;
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else buffer_out0[data_cnt[8:1]] <= din;
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end
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end
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end
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// ... advance counter on falling edge
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always @(posedge clk) begin
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if(phase == `PHASE_IDLE) cmd_cnt <= 4'd0;
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else if(stb_adv && (phase == `PHASE_CMD_IN) && (cmd_cnt != 15)) cmd_cnt <= cmd_cnt + 4'd1;
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end
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// count data bytes. don't increase counter while we are waiting for data from
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// the io controller
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reg [31:0] data_cnt;
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reg data_complete;
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// For block transfers tlen contains the number of 512 bytes blocks to transfer.
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// Most other commands have the bytes length stored in the transfer length field.
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// And some have a fixed length idependent from any header field.
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// The data transfer has finished once the data counter reaches this
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// number.
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wire [31:0] data_len =
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cmd_read_capacity?32'd8:
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cmd_read?{ 7'd0, tlen, 9'd0 }: // read command length is in 512 bytes blocks
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cmd_write?{ 7'd0, tlen, 9'd0 }: // write command length is in 512 bytes blocks
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{ 16'd0, tlen }; // inquiry etc have length in bytes
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always @(posedge clk) begin
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if((phase != `PHASE_DATA_OUT) && (phase != `PHASE_DATA_IN) && (phase != `PHASE_STATUS_OUT) && (phase != `PHASE_MESSAGE_OUT)) begin
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data_cnt <= 0;
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data_complete <= 0;
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end else begin
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if(stb_adv)begin
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if(!data_complete) data_cnt <= data_cnt + 1'd1;
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data_complete <= (data_len - 1'd1) == data_cnt;
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end
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end
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end
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// check whether status byte has been sent
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reg status_sent;
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always @(posedge clk) begin
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if(phase != `PHASE_STATUS_OUT) status_sent <= 0;
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else if(stb_adv) status_sent <= 1;
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end
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// check whether message byte has been sent
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reg message_sent;
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always @(posedge clk) begin
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if(phase != `PHASE_MESSAGE_OUT) message_sent <= 0;
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else if(stb_adv) message_sent <= 1;
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end
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/* ----------------------- command decoding ------------------------------- */
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// parse commands
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wire [7:0] op_code = cmd[0];
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wire [2:0] cmd_group = op_code[7:5];
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// check if a complete command has been received
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wire cmd_cpl = cmd6_cpl || cmd10_cpl;
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wire cmd6_cpl = (cmd_group == 3'b000) && (cmd_cnt == 6);
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wire cmd10_cpl = ((cmd_group == 3'b010) || (cmd_group == 3'b001)) && (cmd_cnt == 10);
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// https://en.wikipedia.org/wiki/SCSI_command
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wire cmd_read = cmd_read6 || cmd_read10;
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wire cmd_read6 = (op_code == 8'h08);
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wire cmd_read10 = (op_code == 8'h28);
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wire cmd_write = cmd_write6 || cmd_write10;
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wire cmd_write6 = (op_code == 8'h0a);
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wire cmd_write10 = (op_code == 8'h2a);
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wire cmd_inquiry = (op_code == 8'h12);
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wire cmd_format = (op_code == 8'h04);
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wire cmd_mode_select = (op_code == 8'h15);
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wire cmd_mode_sense = (op_code == 8'h1a);
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wire cmd_test_unit_ready = (op_code == 8'h00);
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wire cmd_read_capacity = (op_code == 8'h25);
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wire cmd_read_buffer = (op_code == 8'h3b); // fake
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wire cmd_write_buffer = (op_code == 8'h3c); // fake
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// valid command in buffer? TODO: check for valid command parameters
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wire cmd_ok = cmd_read || cmd_write || cmd_inquiry || cmd_test_unit_ready ||
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cmd_read_capacity || cmd_mode_select || cmd_format || cmd_mode_sense ||
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cmd_read_buffer | cmd_write_buffer;
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// latch parameters once command is complete
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reg [31:0] lba;
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reg [15:0] tlen;
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always @(posedge clk) begin
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if(cmd_cpl && (phase == `PHASE_CMD_IN)) begin
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lba <= cmd6_cpl?{11'd0, lba6}:lba10;
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tlen <= cmd6_cpl?{7'd0, tlen6}:tlen10;
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end
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end
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// logical block address
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wire [7:0] cmd1 = cmd[1];
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wire [20:0] lba6 = { cmd1[4:0], cmd[2], cmd[3] };
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wire [31:0] lba10 = { cmd[2], cmd[3], cmd[4], cmd[5] };
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// transfer length
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wire [8:0] tlen6 = (cmd[4] == 0)?9'd256:{1'b0,cmd[4]};
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wire [15:0] tlen10 = { cmd[7], cmd[8] };
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// the 5380 changes phase in the falling edge, thus we monitor it
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// on the rising edge
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always @(posedge clk) begin
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if(rst) begin
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phase <= `PHASE_IDLE;
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end else begin
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if(phase == `PHASE_IDLE) begin
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if(sel && din[ID]) // own id on bus during selection?
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phase <= `PHASE_CMD_IN;
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end
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else if(phase == `PHASE_CMD_IN) begin
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// check if a full command is in the buffer
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if(cmd_cpl) begin
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// is this a supported and valid command?
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if(cmd_ok) begin
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// yes, continue
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status <= `STATUS_OK;
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// continue according to command
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// these commands return data
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if(cmd_read || cmd_inquiry || cmd_read_capacity || cmd_mode_sense || cmd_read_buffer) phase <= `PHASE_DATA_OUT;
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// these commands receive dataa
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else if(cmd_write || cmd_mode_select || cmd_write_buffer) phase <= `PHASE_DATA_IN;
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// and all other valid commands are just "ok"
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else phase <= `PHASE_STATUS_OUT;
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end else begin
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// no, report failure
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status <= `STATUS_CHECK_CONDITION;
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phase <= `PHASE_STATUS_OUT;
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end
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end
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end
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else if(phase == `PHASE_DATA_OUT) begin
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if(data_complete) phase <= `PHASE_STATUS_OUT;
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end
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else if(phase == `PHASE_DATA_IN) begin
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if(data_complete) phase <= `PHASE_STATUS_OUT;
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end
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else if(phase == `PHASE_STATUS_OUT) begin
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if(status_sent) phase <= `PHASE_MESSAGE_OUT;
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end
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else if(phase == `PHASE_MESSAGE_OUT) begin
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if(message_sent) phase <= `PHASE_IDLE;
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end
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else
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phase <= `PHASE_IDLE; // should never happen
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end
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end
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endmodule
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