287 lines
7.5 KiB
Verilog
287 lines
7.5 KiB
Verilog
// A simple OSD implementation. Can be hooked up between a cores
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// VGA output and the physical VGA pins
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module osd
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(
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input clk_sys,
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input io_osd,
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input io_strobe,
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input [15:0] io_din,
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input clk_video,
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input [23:0] din,
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input de_in,
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input vs_in,
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input hs_in,
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output [23:0] dout,
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output reg de_out,
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output reg vs_out,
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output reg hs_out,
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output reg osd_status
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);
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parameter OSD_COLOR = 3'd4;
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localparam OSD_WIDTH = 12'd256;
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localparam OSD_HEIGHT = 12'd64;
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`ifdef OSD_HEADER
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localparam OSD_HDR = 12'd24;
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`else
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localparam OSD_HDR = 12'd0;
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`endif
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reg osd_enable;
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(* ramstyle="no_rw_check" *) reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096];
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reg info = 0;
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reg [8:0] infoh;
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reg [8:0] infow;
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reg [21:0] infox;
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reg [21:0] infoy;
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reg [21:0] osd_h;
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reg [21:0] osd_t;
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reg [21:0] osd_w;
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reg [1:0] rot = 0;
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always@(posedge clk_sys) begin
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reg [12:0] bcnt;
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reg [7:0] cmd;
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reg has_cmd;
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reg old_strobe;
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reg highres = 0;
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osd_t <= rot[0] ? OSD_WIDTH : (OSD_HEIGHT<<1);
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osd_h <= rot[0] ? (info ? infow : OSD_WIDTH) : info ? infoh : (OSD_HEIGHT<<highres);
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osd_w <= rot[0] ? (info ? infoh : (OSD_HEIGHT<<highres)) : (info ? infow : OSD_WIDTH);
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old_strobe <= io_strobe;
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if(~io_osd) begin
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bcnt <= 0;
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has_cmd <= 0;
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cmd <= 0;
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if(cmd[7:4] == 4) osd_enable <= cmd[0];
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end else begin
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if(~old_strobe & io_strobe) begin
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if(!has_cmd) begin
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has_cmd <= 1;
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cmd <= io_din[7:0];
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// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
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if(io_din[7:4] == 4) begin
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if(!io_din[0]) {osd_status,highres} <= 0;
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else {osd_status,info} <= {~io_din[2] & ~io_din[3],io_din[2]};
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bcnt <= 0;
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end
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// command 0x20: OSDCMDWRITE
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if(io_din[7:5] == 'b001) begin
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if(io_din[3]) highres <= 1;
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bcnt <= {io_din[4:0], 8'h00};
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end
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end else begin
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// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
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if(cmd[7:4] == 4) begin
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if(bcnt == 0) infox <= io_din[11:0];
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if(bcnt == 1) infoy <= io_din[11:0];
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if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
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if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
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if(bcnt == 4) rot <= io_din[1:0];
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end
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// command 0x20: OSDCMDWRITE
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if(cmd[7:5] == 'b001) osd_buffer[bcnt] <= io_din[7:0];
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bcnt <= bcnt + 1'd1;
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end
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end
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end
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end
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(* direct_enable *) reg ce_pix;
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always @(posedge clk_video) begin
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reg [21:0] cnt = 0;
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reg [21:0] pixsz, pixcnt;
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reg deD;
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cnt <= cnt + 1'd1;
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deD <= de_in;
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pixcnt <= pixcnt + 1'd1;
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if(pixcnt == pixsz) pixcnt <= 0;
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ce_pix <= !pixcnt;
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if(~deD && de_in) cnt <= 0;
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if(deD && ~de_in) begin
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pixsz <= (((cnt+1'b1) >> (9-rot[0])) > 1) ? (((cnt+1'b1) >> (9-rot[0])) - 1'd1) : 22'd0;
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pixcnt <= 0;
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end
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end
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reg [2:0] osd_de;
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reg osd_pixel;
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reg [21:0] v_cnt;
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reg v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4;
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reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5;
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reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5;
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wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
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// pipeline the comparisons a bit
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always @(posedge clk_video) if(ce_pix) begin
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v_cnt_h <= v_cnt <= osd_t;
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v_cnt_1 <= v_cnt < 320;
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v_cnt_2 <= v_cnt < 640;
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v_cnt_3 <= v_cnt < 960;
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v_cnt_4 <= v_cnt < 1280;
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v_osd_start_h <= (v_cnt-(osd_h_hdr>>1))>>1;
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v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1;
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v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1;
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v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1;
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v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1;
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v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1;
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v_info_start_h <= rot[0] ? infox : infoy;
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v_info_start_1 <= rot[0] ? infox : infoy;
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v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1);
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v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1));
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v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2);
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v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2));
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end
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always @(posedge clk_video) begin
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reg deD;
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reg [2:0] osd_div;
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reg [2:0] multiscan;
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reg [7:0] osd_byte;
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reg [23:0] h_cnt;
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reg [21:0] dsp_width;
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reg [21:0] osd_vcnt;
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reg [21:0] h_osd_start;
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reg [21:0] v_osd_start;
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reg [21:0] osd_hcnt;
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reg [21:0] osd_hcnt2;
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reg osd_de1,osd_de2;
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reg [1:0] osd_en;
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reg f1;
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reg half;
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if(ce_pix) begin
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deD <= de_in;
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if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
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if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
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if(~&osd_hcnt2) osd_hcnt2 <= osd_hcnt2 + 1'd1;
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if (h_cnt == h_osd_start) begin
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osd_de[0] <= osd_en[1] && osd_h && (
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osd_vcnt[11] ? (osd_vcnt[7] && (osd_vcnt[6:0] >= 4) && (osd_vcnt[6:0] < 19)) :
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(info && (rot == 3)) ? !osd_vcnt[21:8] :
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(osd_vcnt < osd_h)
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);
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osd_hcnt <= 0;
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osd_hcnt2 <= 0;
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if(info && rot == 1) osd_hcnt2 <= 22'd128-infoh;
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end
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if (osd_hcnt+1 == osd_w) osd_de[0] <= 0;
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// falling edge of de
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if(!de_in && deD) dsp_width <= h_cnt[21:0];
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// rising edge of de
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if(de_in && !deD) begin
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h_cnt <= 0;
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v_cnt <= v_cnt + 1'd1;
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h_osd_start <= info ? (rot[0] ? infoy : infox) : (((dsp_width - osd_w)>>1) - 2'd2);
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if(h_cnt > {dsp_width, 2'b00}) begin
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v_cnt <= 1;
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f1 <= ~f1; // skip every other frame for interlace compatibility.
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if(~f1) begin
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osd_en <= (osd_en << 1) | osd_enable;
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if(~osd_enable) osd_en <= 0;
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half <= 0;
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if(v_cnt_h) begin
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multiscan <= 0;
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v_osd_start <= info ? v_info_start_h : v_osd_start_h;
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half <= 1;
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end
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else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin
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multiscan <= 0;
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v_osd_start <= info ? v_info_start_1 : v_osd_start_1;
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end
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else if(rot[0] ? v_cnt_3 : v_cnt_2) begin
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multiscan <= 1;
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v_osd_start <= info ? v_info_start_2 : v_osd_start_2;
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end
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else if(rot[0] ? v_cnt_4 : v_cnt_3) begin
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multiscan <= 2;
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v_osd_start <= info ? v_info_start_3 : v_osd_start_3;
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end
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else if(rot[0] | v_cnt_4) begin
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multiscan <= 3;
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v_osd_start <= info ? v_info_start_4 : v_osd_start_4;
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end
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else begin
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multiscan <= 4;
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v_osd_start <= info ? v_info_start_5 : v_osd_start_5;
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end
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end
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end
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osd_div <= osd_div + 1'd1;
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if(osd_div == multiscan) begin
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osd_div <= 0;
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if(~osd_vcnt[10]) osd_vcnt <= osd_vcnt + 1'd1 + half;
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if(osd_vcnt == 'b100010011111 && ~info) osd_vcnt <= 0;
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end
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if(v_osd_start == v_cnt) begin
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{osd_div,osd_vcnt} <= 0;
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if(info && rot == 3) osd_vcnt <= 22'd256-infow;
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else if(OSD_HDR && !rot) osd_vcnt <= {~info, 3'b000, ~info, 7'b0000000};
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end
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end
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osd_byte <= osd_buffer[rot[0] ? ({osd_hcnt2[6:3], osd_vcnt[7:0]} ^ { {4{~rot[1]}}, {8{rot[1]}} }) : {osd_vcnt[7:3], osd_hcnt[7:0]}];
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osd_pixel <= osd_byte[rot[0] ? ((osd_hcnt2[2:0]-1'd1) ^ {3{~rot[1]}}) : osd_vcnt[2:0]];
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osd_de[2:1] <= osd_de[1:0];
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end
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end
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reg [23:0] rdout;
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assign dout = rdout;
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always @(posedge clk_video) begin
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reg [23:0] ordout1, nrdout1, rdout2, rdout3;
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reg de1,de2,de3;
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reg osd_mux;
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reg vs1,vs2,vs3;
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reg hs1,hs2,hs3;
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nrdout1 <= din;
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ordout1 <= {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},// 23:16
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{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},// 15:8
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{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; // 7:0
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osd_mux <= ~osd_de[2];
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rdout2 <= osd_mux ? nrdout1 : ordout1;
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rdout3 <= rdout2;
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de1 <= de_in; de2 <= de1; de3 <= de2;
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hs1 <= hs_in; hs2 <= hs1; hs3 <= hs2;
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vs1 <= vs_in; vs2 <= vs1; vs3 <= vs2;
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rdout <= rdout3;
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de_out <= de3;
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hs_out <= hs3;
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vs_out <= vs3;
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end
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endmodule
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