163 lines
3.4 KiB
Systemverilog
163 lines
3.4 KiB
Systemverilog
//============================================================================
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//
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// LTC2308 controller
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// Copyright (C) 2019 Sorgelig
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//
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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// NUM_CH 1..8
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// Sampling rate = ADC_RATE/NUM_CH
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// ADC_RATE max is ~500KHz
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// CLK_RATE max is ~80MHz
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module ltc2308 #(parameter NUM_CH = 2, ADC_RATE = 96000, CLK_RATE = 50000000)
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(
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input reset,
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input clk,
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inout [3:0] ADC_BUS,
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output reg dout_sync, // toggle with every ADC round
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output reg [(NUM_CH*12)-1:0] dout // 12 bits per channel (unsigned)
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);
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localparam TCONV = CLK_RATE/625000;
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reg sck;
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wire sdo = cfg[5];
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assign ADC_BUS[3] = sck;
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wire sdi = ADC_BUS[2];
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assign ADC_BUS[1] = sdo;
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assign ADC_BUS[0] = convst;
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reg convst;
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reg [5:0] cfg;
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reg [31:0] sum;
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wire [31:0] next_sum = sum + ADC_RATE;
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reg [2:0] pin;
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wire [2:0] next_pin = (pin == (NUM_CH-1)) ? 3'd0 : (pin + 1'd1);
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always @(posedge clk) begin
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reg [7:0] tconv;
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reg [3:0] bitcnt;
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reg [10:0] adcin;
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convst <= 0;
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if(reset) begin
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sum <= 0;
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tconv <= 0;
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bitcnt <= 0;
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sck <= 0;
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cfg <= 0;
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dout <= 0;
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pin <= NUM_CH[2:0]-1'd1;
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end
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else begin
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sum <= next_sum;
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if(next_sum >= CLK_RATE) begin
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sum <= next_sum - CLK_RATE;
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tconv <= TCONV[7:0];
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convst <= 1;
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bitcnt <= 12;
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cfg <= {1'b1, next_pin[0], next_pin[2:1], 1'b1, 1'b0};
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if(!next_pin) dout_sync <= ~dout_sync;
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end
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if(tconv) tconv <= tconv - 1'd1;
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else if(bitcnt) begin
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sck <= ~sck;
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if(sck) cfg <= cfg<<1;
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else begin
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adcin <= {adcin[9:0],sdi};
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bitcnt <= bitcnt - 1'd1;
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if(bitcnt == 1) begin
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dout[pin*12 +:12] <= {adcin,sdi};
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pin <= next_pin;
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end
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end
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end
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else sck <= 0;
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end
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end
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endmodule
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module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000)
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(
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input reset,
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input clk,
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inout [3:0] ADC_BUS,
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output reg dout,
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output active
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);
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wire [11:0] adc_data;
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wire adc_sync;
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ltc2308 #(1, ADC_RATE, CLK_RATE) adc
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(
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.reset(reset),
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.clk(clk),
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.ADC_BUS(ADC_BUS),
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.dout(adc_data),
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.dout_sync(adc_sync)
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);
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always @(posedge clk) begin
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reg [13:0] data1,data2,data3,data4, sum;
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reg adc_sync_d;
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adc_sync_d<=adc_sync;
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if(adc_sync_d ^ adc_sync) begin
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data1 <= data2;
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data2 <= data3;
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data3 <= data4;
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data4 <= adc_data;
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sum <= data1+data2+data3+data4;
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if(sum[13:2]<HIST_LOW) dout <= 0;
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if(sum[13:2]>HIST_HIGH) dout <= 1;
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end
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end
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assign active = |act;
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reg [1:0] act;
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always @(posedge clk) begin
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reg [31:0] onesec;
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reg old_dout;
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onesec <= onesec + 1;
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if(onesec>CLK_RATE) begin
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onesec <= 0;
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if(act) act <= act - 1'd1;
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end
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old_dout <= dout;
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if(old_dout ^ dout) act <= 2;
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end
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endmodule
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