595 lines
15 KiB
Systemverilog
595 lines
15 KiB
Systemverilog
//============================================================================
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// Macintosh Plus
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//
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// Port to MiSTer
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// Copyright (C) 2017,2018 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [44:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] VIDEO_ARX,
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output [7:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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input TAPE_IN,
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// SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE
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);
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign LED_USER = dio_download || (disk_act ^ |diskMotor);
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign VIDEO_ARX = status[8] ? 8'd16 : 8'd4;
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assign VIDEO_ARY = status[8] ? 8'd9 : 8'd3;
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`include "build_id.v"
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localparam CONF_STR = {
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"MACPLUS;;",
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"-;",
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"F,DSK;",
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"F,DSK;",
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"S,VHD;",
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"-;",
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"O8,Aspect ratio,4:3,16:9;",
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"-;",
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"O9A,Memory,512KB,1MB,4MB;",
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"O5,Speed,Normal,Turbo;",
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"-;",
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"R6,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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//////////////////// CLOCKS ///////////////////
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wire clk_sys;
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wire pll_locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_sys),
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.outclk_1(SDRAM_CLK),
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.locked(pll_locked)
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);
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wire cep = (stage == 0);
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wire cen = (stage == 4);
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wire cel = (stage == 7);
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wire cepix = !stage[1:0];
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reg [2:0] stage;
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always @(negedge clk_sys) stage <= stage + 1'd1;
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///////////////////////////////////////////////////
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// interconnects
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// CPU
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wire _cpuReset, _cpuResetOut, _cpuUDS, _cpuLDS, _cpuRW;
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wire [2:0] _cpuIPL;
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wire [7:0] cpuAddrHi;
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wire [23:0] cpuAddr;
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wire [15:0] cpuDataOut;
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// RAM/ROM
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wire _romOE;
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wire _ramOE, _ramWE;
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wire _memoryUDS, _memoryLDS;
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wire videoBusControl;
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wire dioBusControl;
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wire cpuBusControl;
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wire [21:0] memoryAddr;
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wire [15:0] memoryDataOut;
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// peripherals
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wire memoryOverlayOn, selectSCSI, selectSCC, selectIWM, selectVIA;
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wire [15:0] dataControllerDataOut;
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// audio
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wire snd_alt;
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wire loadSound;
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// floppy disk image interface
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wire dskReadAckInt;
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wire [21:0] dskReadAddrInt;
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wire dskReadAckExt;
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wire [21:0] dskReadAddrExt;
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wire [1:0] diskMotor, diskAct, diskEject;
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// the status register is controlled by the on screen display (OSD)
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wire [31:0] status;
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wire [1:0] buttons;
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wire [31:0] sd_lba;
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wire sd_rd;
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wire sd_wr;
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wire sd_ack;
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wire [8:0] sd_buff_addr;
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wire [7:0] sd_buff_dout;
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wire [7:0] sd_buff_din;
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wire sd_buff_wr;
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reg ioctl_wr;
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wire ioctl_write;
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reg ioctl_wait = 0;
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wire [10:0] ps2_key;
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wire [24:0] ps2_mouse;
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wire capslock;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_data;
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always @(posedge clk_sys) begin
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reg [7:0] temp;
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ioctl_wr <= 0;
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if(ioctl_write) begin
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if(~ioctl_addr[0]) temp <= ioctl_data;
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else begin
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dio_data <= {temp, ioctl_data};
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ioctl_wr <= 1;
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end
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end
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end
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hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.buttons(buttons),
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.status(status),
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.sd_lba(sd_lba),
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.sd_rd(sd_rd),
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.sd_wr(sd_wr),
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.sd_ack(sd_ack),
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.sd_conf(0),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(sd_buff_din),
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.sd_buff_wr(sd_buff_wr),
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.ioctl_download(dio_download),
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.ioctl_index(dio_index),
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.ioctl_wr(ioctl_write),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_data),
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.ioctl_wait(ioctl_wait),
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.ps2_key(ps2_key),
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.ps2_kbd_led_use(3'b001),
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.ps2_kbd_led_status({2'b00, capslock}),
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.ps2_mouse(ps2_mouse)
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);
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wire [1:0] cpu_busstate;
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wire cpu_clkena = cep && (cpuBusControl || (cpu_busstate == 2'b01));
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reg [15:0] cpuDataIn;
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always @(posedge clk_sys) if(cel && cpuBusControl && ~cpu_busstate[0] && _cpuRW) cpuDataIn <= dataControllerDataOut;
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TG68KdotC_Kernel #(0,0,0,0,0,0) m68k
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(
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.clk ( clk_sys ),
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.nReset ( _cpuReset ),
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.clkena_in ( cpu_clkena ),
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.data_in ( cpuDataIn ),
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.IPL ( _cpuIPL ),
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.IPL_autovector ( 1'b1 ),
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.berr ( 1'b0 ),
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.clr_berr ( 1'b0 ),
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.CPU ( 2'b00 ), // 00=68000
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.addr ( {cpuAddrHi, cpuAddr} ),
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.data_write ( cpuDataOut ),
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.nUDS ( _cpuUDS ),
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.nLDS ( _cpuLDS ),
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.nWr ( _cpuRW ),
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.busstate ( cpu_busstate ), // 00-> fetch code 10->read data 11->write data 01->no memaccess
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.nResetOut ( _cpuResetOut ),
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.FC ( )
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);
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assign VGA_R = {8{pixelOut}};
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assign VGA_G = {8{pixelOut}};
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assign VGA_B = {8{pixelOut}};
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assign CLK_VIDEO = clk_sys;
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assign CE_PIXEL = cepix;
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wire screenWrite;
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always @(*) begin
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case(configRAMSize)
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0: screenWrite = ~_ramWE && &memoryAddr[16:15]; // 01A700 (018000)
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1: screenWrite = ~_ramWE && &memoryAddr[18:15]; // 07A700 (078000)
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2: screenWrite = ~_ramWE && &memoryAddr[19:15]; // 0FA700 (0F8000)
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3: screenWrite = ~_ramWE && &memoryAddr[21:15]; // 3FA700 (3F8000)
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endcase
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end
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wire pixelOut, _hblank, _vblank;
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video video
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(
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.clk(clk_sys),
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.ce(cepix),
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.addr(cpuAddr[15:1]),
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.dataIn(cpuDataOut),
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.wr({~_cpuUDS & screenWrite, ~_cpuLDS & screenWrite}),
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._hblank(_hblank),
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._vblank(_vblank),
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.hsync(VGA_HS),
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.vsync(VGA_VS),
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.video_en(VGA_DE),
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.pixelOut(pixelOut)
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);
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wire [10:0] audio;
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assign AUDIO_L = {audio[10:0], 5'b00000};
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assign AUDIO_R = {audio[10:0], 5'b00000};
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assign AUDIO_S = 0;
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assign AUDIO_MIX = 0;
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wire status_turbo = status[5];
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wire status_reset = status[6];
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wire [1:0] status_mem = status[10:9]; // 128KB, 512KB, 1MB, 4MB
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reg [1:0] configRAMSize= 3;
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reg n_reset = 0;
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always @(posedge clk_sys) begin
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reg [15:0] rst_cnt;
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// various sources can reset the mac
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if(!pll_locked || status[0] || status_reset || buttons[1] || RESET || ~_cpuResetOut) begin
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rst_cnt <= '1;
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n_reset <= 0;
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end else if(rst_cnt) begin
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if(cen) rst_cnt <= rst_cnt - 1'd1;
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configRAMSize <= status_mem + 1'd1;
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end else n_reset <= 1;
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end
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addrController_top ac0
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(
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.clk(clk_sys),
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.cep(cep),
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.cen(cen),
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.cpuAddr(cpuAddr),
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._cpuUDS(_cpuUDS),
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._cpuLDS(_cpuLDS),
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._cpuRW(_cpuRW),
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.turbo(real_turbo),
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.configROMSize(1), // 128KB
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.configRAMSize(configRAMSize),
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.memoryAddr(memoryAddr),
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._memoryUDS(_memoryUDS),
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._memoryLDS(_memoryLDS),
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._romOE(_romOE),
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._ramOE(_ramOE),
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._ramWE(_ramWE),
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.dioBusControl(dioBusControl),
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.cpuBusControl(cpuBusControl),
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.selectSCSI(selectSCSI),
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.selectSCC(selectSCC),
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.selectIWM(selectIWM),
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.selectVIA(selectVIA),
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._vblank(_vblank),
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._hblank(_hblank),
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.memoryOverlayOn(memoryOverlayOn),
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.snd_alt(snd_alt),
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.loadSound(loadSound),
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.dskReadAddrInt(dskReadAddrInt),
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.dskReadAckInt(dskReadAckInt),
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.dskReadAddrExt(dskReadAddrExt),
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.dskReadAckExt(dskReadAckExt)
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);
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dataController_top dc0
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(
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.clk(clk_sys),
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.cep(cep),
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.cen(cen),
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._systemReset(n_reset),
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._cpuReset(_cpuReset),
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._cpuIPL(_cpuIPL),
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._cpuUDS(_cpuUDS),
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._cpuLDS(_cpuLDS),
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._cpuRW(_cpuRW),
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.cpuDataIn(cpuDataOut),
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.cpuDataOut(dataControllerDataOut),
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.cpuAddrRegHi(cpuAddr[12:9]),
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.cpuAddrRegMid(cpuAddr[6:4]), // for SCSI
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.cpuAddrRegLo(cpuAddr[2:1]),
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.selectSCSI(selectSCSI),
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.selectSCC(selectSCC),
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.selectIWM(selectIWM),
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.selectVIA(selectVIA),
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.cpuBusControl(cpuBusControl),
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.memoryDataOut(memoryDataOut),
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.memoryDataIn(sdram_do),
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// peripherals
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.ps2_key(ps2_key),
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.capslock(capslock),
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.ps2_mouse(ps2_mouse),
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.serialIn(0),
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// video
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._hblank(_hblank),
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._vblank(_vblank),
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.memoryOverlayOn(memoryOverlayOn),
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.audioOut(audio),
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.snd_alt(snd_alt),
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.loadSound(loadSound),
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// floppy disk interface
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.insertDisk({dsk_ext_ins, dsk_int_ins}),
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.diskSides({dsk_ext_ds, dsk_int_ds}),
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.diskEject(diskEject),
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.dskReadAddrInt(dskReadAddrInt),
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.dskReadAckInt(dskReadAckInt),
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.dskReadAddrExt(dskReadAddrExt),
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.dskReadAckExt(dskReadAckExt),
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.diskMotor(diskMotor),
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.diskAct(diskAct),
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// block device interface for scsi disk
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.io_lba(sd_lba),
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.io_rd(sd_rd),
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.io_wr(sd_wr),
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.io_ack(sd_ack),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(sd_buff_din),
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.sd_buff_wr(sd_buff_wr)
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);
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reg disk_act;
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always @(posedge clk_sys) begin
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integer timeout = 0;
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if(timeout) begin
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timeout <= timeout - 1;
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disk_act <= 1;
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end else begin
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disk_act <= 0;
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end
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if(|diskAct) timeout <= 1000000;
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end
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//////////////////////// DOWNLOADING ///////////////////////////
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// include ROM download helper
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wire dio_download;
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reg dio_write;
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wire [23:0] dio_addr = ioctl_addr[24:1];
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wire [7:0] dio_index;
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reg [15:0] dio_data;
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// good floppy image sizes are 819200 bytes and 409600 bytes
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reg dsk_int_ds, dsk_ext_ds; // double sided image inserted
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reg dsk_int_ss, dsk_ext_ss; // single sided image inserted
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// any known type of disk image inserted?
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wire dsk_int_ins = dsk_int_ds || dsk_int_ss;
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wire dsk_ext_ins = dsk_ext_ds || dsk_ext_ss;
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// at the end of a download latch file size
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// diskEject is set by macos on eject
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always @(posedge clk_sys) begin
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reg old_down;
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old_down <= dio_download;
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if(old_down && ~dio_download && dio_index == 1) begin
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dsk_int_ds <= (dio_addr == 409600); // double sides disk, addr counts words, not bytes
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dsk_int_ss <= (dio_addr == 204800); // single sided disk
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end
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if(diskEject[0]) begin
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dsk_int_ds <= 0;
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dsk_int_ss <= 0;
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end
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end
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always @(posedge clk_sys) begin
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reg old_down;
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old_down <= dio_download;
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if(old_down && ~dio_download && dio_index == 2) begin
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dsk_ext_ds <= (dio_addr == 409600); // double sided disk, addr counts words, not bytes
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dsk_ext_ss <= (dio_addr == 204800); // single sided disk
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end
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if(diskEject[1]) begin
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dsk_ext_ds <= 0;
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dsk_ext_ss <= 0;
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end
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end
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// disk images are being stored right after os rom at word offset 0x80000 and 0x100000
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wire [20:0] dio_a =
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(dio_index == 0)?dio_addr[20:0]: // os rom
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(dio_index == 1)?{21'h80000 + dio_addr[20:0]}: // first dsk image at 512k word addr
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{21'h100000 + dio_addr[20:0]}; // second dsk image at 1M word addr
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|
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always @(posedge clk_sys) begin
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reg old_cyc = 0;
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|
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old_cyc <= dioBusControl;
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if(ioctl_wr) ioctl_wait <= 1;
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|
|
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if(~dioBusControl) dio_write <= ioctl_wait;
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if(old_cyc & ~dioBusControl & dio_write) ioctl_wait <= 0;
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end
|
|
|
|
// sdram used for ram/rom maps directly into 68k address space
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|
wire download_cycle = dio_download && dioBusControl;
|
|
|
|
////////////////////////// SDRAM /////////////////////////////////
|
|
|
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wire [24:0] sdram_addr = download_cycle ? { 4'b0001, dio_a[20:0] } : { 3'b000, ~_romOE, memoryAddr[21:1] };
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|
wire [15:0] sdram_din = download_cycle ? dio_data : memoryDataOut;
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wire [1:0] sdram_ds = download_cycle ? 2'b11 : { !_memoryUDS, !_memoryLDS };
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|
wire sdram_we = download_cycle ? dio_write : !_ramWE;
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wire sdram_oe = download_cycle ? 1'b0 : (!_ramOE || !_romOE);
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|
wire [15:0] sdram_do = download_cycle ? 16'hffff : (dskReadAckInt || dskReadAckExt) ? extra_rom_data_demux : sdram_out;
|
|
|
|
// "extra rom" is used to hold the disk image. It's expected to be byte wide and
|
|
// we thus need to properly demultiplex the word returned from sdram in that case
|
|
wire [15:0] extra_rom_data_demux = memoryAddr[0]? {sdram_out[7:0],sdram_out[7:0]}:{sdram_out[15:8],sdram_out[15:8]};
|
|
wire [15:0] sdram_out;
|
|
|
|
assign SDRAM_CKE = 1;
|
|
|
|
sdram sdram
|
|
(
|
|
// system interface
|
|
.init ( !pll_locked ),
|
|
.clk ( clk_sys ),
|
|
.sync ( cep ),
|
|
|
|
// interface to the MT48LC16M16 chip
|
|
.sd_data ( SDRAM_DQ ),
|
|
.sd_addr ( SDRAM_A ),
|
|
.sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ),
|
|
.sd_cs ( SDRAM_nCS ),
|
|
.sd_ba ( SDRAM_BA ),
|
|
.sd_we ( SDRAM_nWE ),
|
|
.sd_ras ( SDRAM_nRAS ),
|
|
.sd_cas ( SDRAM_nCAS ),
|
|
|
|
// cpu/chipset interface
|
|
// map rom to sdram word address $200000 - $20ffff
|
|
.din ( sdram_din ),
|
|
.addr ( sdram_addr ),
|
|
.ds ( sdram_ds ),
|
|
.we ( sdram_we ),
|
|
.oe ( sdram_oe ),
|
|
.dout ( sdram_out )
|
|
);
|
|
|
|
|
|
//////////////////////// TURBO HANDLING //////////////////////////
|
|
|
|
// cannot boot from SCSI if turbo enabled
|
|
// delay the turbo.
|
|
reg real_turbo = 0;
|
|
always @(posedge clk_sys) begin
|
|
reg old_ack;
|
|
integer ack_cnt = 0;
|
|
|
|
old_ack <= sd_ack;
|
|
if(old_ack && ~sd_ack && ack_cnt) ack_cnt <= ack_cnt - 1'd1;
|
|
|
|
//Cancel delay if FDD is accesed.
|
|
if(diskMotor) ack_cnt <= 0;
|
|
if(!ack_cnt && dioBusControl) real_turbo <= status_turbo;
|
|
|
|
if(~n_reset) begin
|
|
real_turbo <= 0;
|
|
ack_cnt <= 20;
|
|
end
|
|
end
|
|
|
|
endmodule
|