152 lines
4.6 KiB
Verilog
152 lines
4.6 KiB
Verilog
module addrController_top
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(
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// clocks:
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input clk,
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input cep, // 8.125 MHz CPU clock
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input cen, // 8.125 MHz CPU clock
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// system config:
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input turbo, // 0 = normal, 1 = faster
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input configROMSize, // 0 = 64K ROM, 1 = 128K ROM
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input [1:0] configRAMSize, // 0 = 128K, 1 = 512K, 2 = 1MB, 3 = 4MB RAM
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// 68000 CPU memory interface:
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input [23:0] cpuAddr,
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input _cpuUDS,
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input _cpuLDS,
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input _cpuRW,
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// RAM/ROM:
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output [21:0] memoryAddr,
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output _memoryUDS,
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output _memoryLDS,
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output _romOE,
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output _ramOE,
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output _ramWE,
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output dioBusControl,
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output cpuBusControl,
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// peripherals:
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output selectSCSI,
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output selectSCC,
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output selectIWM,
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output selectVIA,
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// video:
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input _vblank,
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input _hblank,
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input snd_alt,
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output loadSound,
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// misc
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input memoryOverlayOn,
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// interface to read dsk image from ram
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input [21:0] dskReadAddrInt,
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output dskReadAckInt,
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input [21:0] dskReadAddrExt,
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output dskReadAckExt
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);
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// -------------- audio engine (may be moved into seperate module) ---------------
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assign loadSound = audioReq & sndReadAck;
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reg [21:0] audioAddr;
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reg audioReq;
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always @(posedge clk) begin
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reg vblankD;
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reg hblankD;
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reg swap;
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reg sndReadAckD;
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sndReadAckD <= sndReadAck;
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if(sndReadAckD & ~sndReadAck) begin // prepare for next audio cycle
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vblankD <= _vblank;
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hblankD <= _hblank;
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audioReq <= 0;
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// falling adge of _vblank = begin of vblank phase
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if(vblankD && !_vblank) swap <= 1;
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if(hblankD && !_hblank) begin
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if(swap) audioAddr <= snd_alt ? 22'h3FA100 : 22'h3FFD00;
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else audioAddr <= audioAddr + 22'd2;
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swap <= 0;
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audioReq <= 1;
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end
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end
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end
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// interleaved RAM access for CPU and periphery
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reg [3:0] cycle;
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wire [1:0] busCycle = cycle[1:0];
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wire [1:0] subCycle = cycle[3:2];
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always @(posedge clk) if(cep) cycle <= cycle + 2'd1;
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assign cpuBusControl = turbo ? busCycle[0] : (busCycle == 1);
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assign dioBusControl = (busCycle == 2);
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assign dskReadAckInt = dioBusControl && (subCycle == 0);
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assign dskReadAckExt = dioBusControl && (subCycle == 1);
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wire sndReadAck = (busCycle == 0);
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// interconnects
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wire selectRAM, selectROM;
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// RAM/ROM control signals
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wire extraRomRead = dskReadAckInt || dskReadAckExt;
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assign _romOE = ~(extraRomRead || (cpuBusControl && selectROM && _cpuRW));
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assign _ramOE = ~(loadSound || (cpuBusControl && selectRAM && _cpuRW));
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assign _ramWE = ~(cpuBusControl && selectRAM && !_cpuRW);
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assign _memoryUDS = cpuBusControl ? _cpuUDS : 1'b0;
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assign _memoryLDS = cpuBusControl ? _cpuLDS : 1'b0;
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wire [21:0] addrMux = loadSound ? audioAddr : cpuAddr[21:0];
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wire [21:0] macAddr;
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assign macAddr[15:0] = addrMux[15:0];
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// video and sound always addresses ram
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wire ram_access = (cpuBusControl && selectRAM) || loadSound;
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wire rom_access = (cpuBusControl && selectROM);
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// simulate smaller RAM/ROM sizes
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assign macAddr[16] = rom_access && configROMSize == 1'b0 ? 1'b0 : // force A16 to 0 for 64K ROM access
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addrMux[16];
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assign macAddr[17] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A17 to 0 for 128K RAM access
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rom_access && configROMSize == 1'b1 ? 1'b0 : // force A17 to 0 for 128K ROM access
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rom_access && configROMSize == 1'b0 ? 1'b1 : // force A17 to 1 for 64K ROM access (64K ROM image is at $20000)
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addrMux[17];
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assign macAddr[18] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A18 to 0 for 128K RAM access
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rom_access ? 1'b0 : // force A18 to 0 for ROM access
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addrMux[18];
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assign macAddr[19] = ram_access && configRAMSize[1] == 1'b0 ? 1'b0 : // force A19 to 0 for 128K or 512K RAM access
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rom_access ? 1'b0 : // force A19 to 0 for ROM access
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addrMux[19];
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assign macAddr[20] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A20 to 0 for all but 4MB RAM access
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rom_access ? 1'b0 : // force A20 to 0 for ROM access
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addrMux[20];
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assign macAddr[21] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A21 to 0 for all but 4MB RAM access
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rom_access ? 1'b0 : // force A21 to 0 for ROM access
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addrMux[21];
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assign memoryAddr =
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dskReadAckInt ? dskReadAddrInt + 22'h100000: // first dsk image at 1MB
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dskReadAckExt ? dskReadAddrExt + 22'h200000: // second dsk image at 2MB
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macAddr;
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// address decoding
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addrDecoder ad(
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.address(cpuAddr),
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.memoryOverlayOn(memoryOverlayOn),
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.selectRAM(selectRAM),
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.selectROM(selectROM),
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.selectSCSI(selectSCSI),
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.selectSCC(selectSCC),
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.selectIWM(selectIWM),
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.selectVIA(selectVIA));
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endmodule
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