588 lines
14 KiB
Verilog
588 lines
14 KiB
Verilog
`timescale 1ns / 100ps
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/*
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* Zilog 8530 SCC module for minimigmac.
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*
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* Located on high data bus, but writes are done at odd addresses as
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* LDS is used as WR signals or something like that on a Mac Plus.
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*
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* We don't care here and just ignore which side was used.
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*
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* NOTE: We don't implement the 85C30 or ESCC additions such as WR7'
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* for now, it's all very simplified
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*/
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module scc
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(
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input clk,
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input cep,
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input cen,
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input reset_hw,
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/* Bus interface. 2-bit address, to be wired
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* appropriately upstream (to A1..A2).
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*/
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input cs,
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input we,
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input [1:0] rs, /* [1] = data(1)/ctl [0] = a_side(1)/b_side */
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input [7:0] wdata,
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output [7:0] rdata,
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output _irq,
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/* A single serial port on Minimig */
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input rxd,
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output txd,
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input cts, /* normally wired to device DTR output
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* on Mac cables. That same line is also
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* connected to the TRxC input of the SCC
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* to do fast clocking but we don't do that
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* here
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*/
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output rts, /* on a real mac this activates line
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* drivers when low */
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/* DCD for both ports are hijacked by mouse interface */
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input dcd_a, /* We don't synchronize those inputs */
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input dcd_b,
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/* Write request */
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output wreq
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);
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/* Register access is semi-insane */
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reg [3:0] rindex;
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reg [3:0] rindex_latch;
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wire wreg_a;
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wire wreg_b;
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/* Resets via WR9, one clk pulses */
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wire reset_a;
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wire reset_b;
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wire reset;
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/* Data registers */
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reg [7:0] data_a = 0;
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reg [7:0] data_b = 0;
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/* Read registers */
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wire [7:0] rr0_a;
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wire [7:0] rr0_b;
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wire [7:0] rr1_a;
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wire [7:0] rr1_b;
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wire [7:0] rr2_b;
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wire [7:0] rr3_a;
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wire [7:0] rr10_a;
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wire [7:0] rr10_b;
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wire [7:0] rr15_a;
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wire [7:0] rr15_b;
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/* Write registers. Only some are implemented,
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* some result in actions on write and don't
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* store anything
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*/
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reg [7:0] wr1_a;
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reg [7:0] wr1_b;
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reg [7:0] wr2;
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reg [7:0] wr5_a;
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reg [7:0] wr5_b;
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reg [7:0] wr6_a;
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reg [7:0] wr6_b;
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reg [7:0] wr8_a;
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reg [7:0] wr8_b;
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reg [5:0] wr9;
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reg [7:0] wr10_a;
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reg [7:0] wr10_b;
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reg [7:0] wr12_a;
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reg [7:0] wr12_b;
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reg [7:0] wr13_a;
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reg [7:0] wr13_b;
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reg [7:0] wr14_a;
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reg [7:0] wr14_b;
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reg [7:0] wr15_a;
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reg [7:0] wr15_b;
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/* Status latches */
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reg latch_open_a;
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reg latch_open_b;
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reg dcd_latch_a;
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reg dcd_latch_b;
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wire dcd_ip_a;
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wire dcd_ip_b;
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wire do_latch_a;
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wire do_latch_b;
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wire do_extreset_a;
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wire do_extreset_b;
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/* IRQ stuff */
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wire rx_irq_pend_a;
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wire rx_irq_pend_b;
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wire tx_irq_pend_a;
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wire tx_irq_pend_b;
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wire ex_irq_pend_a;
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wire ex_irq_pend_b;
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reg ex_irq_ip_a;
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reg ex_irq_ip_b;
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wire [2:0] rr2_vec_stat;
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/* Register/Data access helpers */
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assign wreg_a = cs & we & (~rs[1]) & rs[0];
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assign wreg_b = cs & we & (~rs[1]) & ~rs[0];
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// make sure rindex changes after the cpu cycle has ended so
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// read data is still stable while cpu advances
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always@(posedge clk) if(cen) rindex <= rindex_latch;
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/* Register index is set by a write to WR0 and reset
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* after any subsequent write. We ignore the side
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*/
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always@(posedge clk or posedge reset) begin
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if (reset)
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rindex_latch <= 0;
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else if (cen && cs && !rs[1]) begin
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/* Default, reset index */
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rindex_latch <= 0;
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/* Write to WR0 */
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if (we && rindex == 0) begin
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/* Get low index bits */
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rindex_latch[2:0] <= wdata[2:0];
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/* Add point high */
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rindex_latch[3] <= (wdata[5:3] == 3'b001);
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end
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end
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end
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/* Reset logic (write to WR9 cmd)
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*
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* Note about resets: Some bits are documented as unchanged/undefined on
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* HW reset by the doc. We apply this to channel and soft resets, however
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* we _do_ reset every bit on an external HW reset in this implementation
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* to make the FPGA & synthesis tools happy.
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*/
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assign reset = ((wreg_a | wreg_b) & (rindex == 9) & (wdata[7:6] == 2'b11)) | reset_hw;
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assign reset_a = ((wreg_a | wreg_b) & (rindex == 9) & (wdata[7:6] == 2'b10)) | reset;
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assign reset_b = ((wreg_a | wreg_b) & (rindex == 9) & (wdata[7:6] == 2'b01)) | reset;
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/* WR1
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* Reset: bit 5 and 2 unchanged */
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr1_a <= 0;
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else if(cen) begin
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if (reset_a)
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wr1_a <= { 2'b00, wr1_a[5], 2'b00, wr1_a[2], 2'b00 };
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else if (wreg_a && rindex == 1)
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wr1_a <= wdata;
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end
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end
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr1_b <= 0;
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else if(cen) begin
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if (reset_b)
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wr1_b <= { 2'b00, wr1_b[5], 2'b00, wr1_b[2], 2'b00 };
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else if (wreg_b && rindex == 1)
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wr1_b <= wdata;
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end
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end
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/* WR2
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* Reset: unchanged
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*/
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr2 <= 0;
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else if (cen && (wreg_a || wreg_b) && rindex == 2)
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wr2 <= wdata;
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end
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/* WR5
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* Reset: Bits 7,4,3,2,1 to 0
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*/
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr5_a <= 0;
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else if(cen) begin
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if (reset_a)
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wr5_a <= { 1'b0, wr5_a[6:5], 4'b0000, wr5_a[0] };
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else if (wreg_a && rindex == 5)
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wr5_a <= wdata;
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end
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end
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr5_b <= 0;
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else if(cen) begin
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if (reset_b)
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wr5_b <= { 1'b0, wr5_b[6:5], 4'b0000, wr5_b[0] };
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else if (wreg_b && rindex == 5)
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wr5_b <= wdata;
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end
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end
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/* WR9. Special: top bits are reset, handled separately, bottom
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* bits are only reset by a hw reset
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*/
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr9 <= 0;
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else if (cen && (wreg_a || wreg_b) && rindex == 9)
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wr9 <= wdata[5:0];
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end
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/* WR10
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* Reset: all 0, except chanel reset retains 6 and 5
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*/
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always@(posedge clk or posedge reset) begin
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if (reset)
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wr10_a <= 0;
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else if(cen) begin
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if (reset_a)
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wr10_a <= { 1'b0, wr10_a[6:5], 5'b00000 };
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else if (wreg_a && rindex == 10)
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wr10_a <= wdata;
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end
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end
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always@(posedge clk or posedge reset) begin
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if (reset)
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wr10_b <= 0;
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else if(cen) begin
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if (reset_b)
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wr10_b <= { 1'b0, wr10_b[6:5], 5'b00000 };
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else if (wreg_b && rindex == 10)
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wr10_b <= wdata;
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end
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end
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/* WR12
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* Reset: Unchanged
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*/
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr12_a <= 0;
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else if (cen && wreg_a && rindex == 12)
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wr12_a <= wdata;
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end
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr12_b <= 0;
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else if (cen && wreg_b && rindex == 12)
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wr12_b <= wdata;
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end
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/* WR13
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* Reset: Unchanged
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*/
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr13_a <= 0;
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else if (cen && wreg_a && rindex == 13)
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wr13_a <= wdata;
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end
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr13_b <= 0;
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else if (cen && wreg_b && rindex == 13)
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wr13_b <= wdata;
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end
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/* WR14
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* Reset: Full reset maintains top 2 bits,
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* Chan reset also maitains bottom 2 bits, bit 4 also
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* reset to a different value
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*/
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr14_a <= 0;
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else if(cen) begin
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if (reset)
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wr14_a <= { wr14_a[7:6], 6'b110000 };
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else if (reset_a)
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wr14_a <= { wr14_a[7:6], 4'b1000, wr14_a[1:0] };
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else if (wreg_a && rindex == 14)
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wr14_a <= wdata;
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end
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end
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always@(posedge clk or posedge reset_hw) begin
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if (reset_hw)
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wr14_b <= 0;
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else if(cen) begin
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if (reset)
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wr14_b <= { wr14_b[7:6], 6'b110000 };
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else if (reset_b)
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wr14_b <= { wr14_b[7:6], 4'b1000, wr14_b[1:0] };
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else if (wreg_b && rindex == 14)
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wr14_b <= wdata;
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end
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end
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/* WR15 */
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always@(posedge clk or posedge reset) begin
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if (reset) begin
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wr15_a <= 8'b11111000;
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wr15_b <= 8'b11111000;
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end else if (cen && rindex == 15) begin
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if(wreg_a) wr15_a <= wdata;
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if(wreg_b) wr15_b <= wdata;
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end
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end
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/* Read data mux */
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assign rdata = rs[1] && rs[0] ? data_a :
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rs[1] ? data_b :
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rindex == 0 && rs[0] ? rr0_a :
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rindex == 0 ? rr0_b :
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rindex == 1 && rs[0] ? rr1_a :
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rindex == 1 ? rr1_b :
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rindex == 2 && rs[0] ? wr2 :
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rindex == 2 ? rr2_b :
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rindex == 3 && rs[0] ? rr3_a :
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rindex == 3 ? 8'h00 :
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rindex == 4 && rs[0] ? rr0_a :
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rindex == 4 ? rr0_b :
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rindex == 5 && rs[0] ? rr1_a :
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rindex == 5 ? rr1_b :
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rindex == 6 && rs[0] ? wr2 :
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rindex == 6 ? rr2_b :
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rindex == 7 && rs[0] ? rr3_a :
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rindex == 7 ? 8'h00 :
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rindex == 8 && rs[0] ? data_a :
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rindex == 8 ? data_b :
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rindex == 9 && rs[0] ? wr13_a :
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rindex == 9 ? wr13_b :
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rindex == 10 && rs[0] ? rr10_a :
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rindex == 10 ? rr10_b :
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rindex == 11 && rs[0] ? rr15_a :
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rindex == 11 ? rr15_b :
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rindex == 12 && rs[0] ? wr12_a :
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rindex == 12 ? wr12_b :
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rindex == 13 && rs[0] ? wr13_a :
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rindex == 13 ? wr13_b :
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rindex == 14 && rs[0] ? rr10_a :
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rindex == 14 ? rr10_b :
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rindex == 15 && rs[0] ? rr15_a :
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rindex == 15 ? rr15_b : 8'hff;
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/* RR0 */
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assign rr0_a = { 1'b0, /* Break */
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1'b1, /* Tx Underrun/EOM */
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1'b0, /* CTS */
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1'b0, /* Sync/Hunt */
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wr15_a[3] ? dcd_latch_a : dcd_a, /* DCD */
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1'b1, /* Tx Empty */
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1'b0, /* Zero Count */
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1'b0 /* Rx Available */
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};
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assign rr0_b = { 1'b0, /* Break */
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1'b1, /* Tx Underrun/EOM */
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1'b0, /* CTS */
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1'b0, /* Sync/Hunt */
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wr15_b[3] ? dcd_latch_b : dcd_b, /* DCD */
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1'b1, /* Tx Empty */
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1'b0, /* Zero Count */
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1'b0 /* Rx Available */
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};
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/* RR1 */
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assign rr1_a = { 1'b0, /* End of frame */
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1'b0, /* CRC/Framing error */
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1'b0, /* Rx Overrun error */
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1'b0, /* Parity error */
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1'b0, /* Residue code 0 */
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1'b1, /* Residue code 1 */
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1'b1, /* Residue code 2 */
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1'b1 /* All sent */
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};
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assign rr1_b = { 1'b0, /* End of frame */
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1'b0, /* CRC/Framing error */
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1'b0, /* Rx Overrun error */
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1'b0, /* Parity error */
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1'b0, /* Residue code 0 */
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1'b1, /* Residue code 1 */
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1'b1, /* Residue code 2 */
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1'b1 /* All sent */
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};
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/* RR2 (Chan B only, A is just WR2) */
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assign rr2_b = { wr2[7],
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wr9[4] ? rr2_vec_stat[0] : wr2[6],
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wr9[4] ? rr2_vec_stat[1] : wr2[5],
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wr9[4] ? rr2_vec_stat[2] : wr2[4],
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wr9[4] ? wr2[3] : rr2_vec_stat[2],
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wr9[4] ? wr2[2] : rr2_vec_stat[1],
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wr9[4] ? wr2[1] : rr2_vec_stat[0],
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wr2[0]
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};
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/* RR3 (Chan A only) */
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assign rr3_a = { 2'b0,
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rx_irq_pend_a, /* Rx interrupt pending */
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tx_irq_pend_a, /* Tx interrupt pending */
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ex_irq_pend_a, /* Status/Ext interrupt pending */
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rx_irq_pend_b,
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tx_irq_pend_b,
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ex_irq_pend_b
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};
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/* RR10 */
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assign rr10_a = { 1'b0, /* One clock missing */
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1'b0, /* Two clocks missing */
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1'b0,
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1'b0, /* Loop sending */
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1'b0,
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1'b0,
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1'b0, /* On Loop */
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1'b0
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};
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assign rr10_b = { 1'b0, /* One clock missing */
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1'b0, /* Two clocks missing */
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1'b0,
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1'b0, /* Loop sending */
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1'b0,
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1'b0,
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1'b0, /* On Loop */
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1'b0
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};
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/* RR15 */
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assign rr15_a = { wr15_a[7],
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wr15_a[6],
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wr15_a[5],
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wr15_a[4],
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wr15_a[3],
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1'b0,
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wr15_a[1],
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1'b0
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};
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assign rr15_b = { wr15_b[7],
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wr15_b[6],
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wr15_b[5],
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wr15_b[4],
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wr15_b[3],
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1'b0,
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wr15_b[1],
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1'b0
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};
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/* Interrupts. Simplified for now
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*
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* Need to add latches. Tx irq is latched when buffer goes from full->empty,
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* it's not a permanent state. For now keep it clear. Will have to fix that.
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*/
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assign rx_irq_pend_a = 0;
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assign tx_irq_pend_a = 0 /*& wr1_a[1]*/; /* Tx always empty for now */
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assign ex_irq_pend_a = ex_irq_ip_a;
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assign rx_irq_pend_b = 0;
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assign tx_irq_pend_b = 0 /*& wr1_b[1]*/; /* Tx always empty for now */
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assign ex_irq_pend_b = ex_irq_ip_b;
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assign _irq = ~(wr9[3] & (rx_irq_pend_a |
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rx_irq_pend_b |
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tx_irq_pend_a |
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tx_irq_pend_b |
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ex_irq_pend_a |
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ex_irq_pend_b));
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/* XXX Verify that... also missing special receive condition */
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assign rr2_vec_stat = rx_irq_pend_a ? 3'b110 :
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tx_irq_pend_a ? 3'b100 :
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ex_irq_pend_a ? 3'b101 :
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rx_irq_pend_b ? 3'b010 :
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tx_irq_pend_b ? 3'b000 :
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ex_irq_pend_b ? 3'b001 : 3'b011;
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/* External/Status interrupt & latch logic */
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assign do_extreset_a = wreg_a & (rindex == 0) & (wdata[5:3] == 3'b010);
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assign do_extreset_b = wreg_b & (rindex == 0) & (wdata[5:3] == 3'b010);
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/* Internal IP bit set if latch different from source and
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* corresponding interrupt is enabled in WR15
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*/
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assign dcd_ip_a = (dcd_a != dcd_latch_a) & wr15_a[3];
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assign dcd_ip_b = (dcd_b != dcd_latch_b) & wr15_b[3];
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/* Latches close when an enabled IP bit is set and latches
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* are currently open
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*/
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assign do_latch_a = latch_open_a & (dcd_ip_a /* | cts... */);
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assign do_latch_b = latch_open_b & (dcd_ip_b /* | cts... */);
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|
|
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/* "Master" interrupt, set when latch close & WR1[0] is set */
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always@(posedge clk or posedge reset) begin
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|
if (reset)
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ex_irq_ip_a <= 0;
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else if(cep) begin
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if (do_extreset_a)
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ex_irq_ip_a <= 0;
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else if (do_latch_a && wr1_a[0])
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ex_irq_ip_a <= 1;
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end
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end
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always@(posedge clk or posedge reset) begin
|
|
if (reset)
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ex_irq_ip_b <= 0;
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else if(cep) begin
|
|
if (do_extreset_b)
|
|
ex_irq_ip_b <= 0;
|
|
else if (do_latch_b && wr1_b[0])
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ex_irq_ip_b <= 1;
|
|
end
|
|
end
|
|
|
|
/* Latch open/close control */
|
|
always@(posedge clk or posedge reset) begin
|
|
if (reset)
|
|
latch_open_a <= 1;
|
|
else if(cep) begin
|
|
if (do_extreset_a)
|
|
latch_open_a <= 1;
|
|
else if (do_latch_a)
|
|
latch_open_a <= 0;
|
|
end
|
|
end
|
|
always@(posedge clk or posedge reset) begin
|
|
if (reset)
|
|
latch_open_b <= 1;
|
|
else if(cep) begin
|
|
if (do_extreset_b)
|
|
latch_open_b <= 1;
|
|
else if (do_latch_b)
|
|
latch_open_b <= 0;
|
|
end
|
|
end
|
|
|
|
/* Latches proper */
|
|
always@(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
dcd_latch_a <= 0;
|
|
/* cts ... */
|
|
end else if(cep) begin
|
|
if (do_latch_a)
|
|
dcd_latch_a <= dcd_a;
|
|
/* cts ... */
|
|
end
|
|
end
|
|
always@(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
dcd_latch_b <= 0;
|
|
/* cts ... */
|
|
end else if(cep) begin
|
|
if (do_latch_b)
|
|
dcd_latch_b <= dcd_b;
|
|
/* cts ... */
|
|
end
|
|
end
|
|
|
|
/* NYI */
|
|
assign txd = 1;
|
|
assign rts = 1;
|
|
|
|
assign wreq = 1;
|
|
endmodule
|