195 lines
6.0 KiB
Systemverilog
195 lines
6.0 KiB
Systemverilog
//
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//
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// sdram controller implementation for the MiST/MiSTer boards
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//
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// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
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// Copyright (c) 2017 Sorgelig
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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// This SDRAM module provides/writes the data in 8 cycles of clock.
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// So, with 64MHz of system clock, it can emulate 8MHz asynchronous DRAM.
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//
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//
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module sdram
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(
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// interface to the MT48LC16M16 chip
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inout [15:0] sd_data, // 16 bit bidirectional data bus
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output reg [12:0] sd_addr, // 13 bit multiplexed address bus
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output reg [1:0] sd_dqm, // two byte masks
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output reg [1:0] sd_ba, // two banks
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output sd_cs, // a single chip select
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output sd_we, // write enable
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output sd_ras, // row address select
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output sd_cas, // columns address select
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// cpu/chipset interface
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input init, // init signal after FPGA config to initialize RAM
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input clk, // sdram is accessed at 64MHz
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input sync,
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input [15:0] din, // data input from chipset/cpu
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output reg [15:0] dout, // data output to chipset/cpu
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input [23:0] addr, // 24 bit word address
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input [1:0] ds, // upper/lower data strobe
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input oe, // cpu/chipset requests read
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input we // cpu/chipset requests write
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);
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localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 3 cycles@128MHz
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localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
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localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
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localparam CAS_LATENCY = 3'd2; // 2/3 allowed
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localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
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localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
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localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
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// ---------------------------------------------------------------------
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// ------------------------ cycle state machine ------------------------
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// ---------------------------------------------------------------------
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// The state machine runs at 128Mhz synchronous to the 8 Mhz chipset clock.
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// It wraps from T15 to T0 on the rising edge of clk_8
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localparam STATE_FIRST = 3'd0; // first state in cycle
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localparam STATE_CMD_START = 3'd1; // state in which a new command can be started
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localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // command can be continued
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localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1;
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localparam STATE_HIGHZ = STATE_READ - 4'd1; // disable output to prevent contention
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// ---------------------------------------------------------------------
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// --------------------------- startup/reset ---------------------------
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// ---------------------------------------------------------------------
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// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
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// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
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reg [4:0] reset;
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always @(posedge clk) begin
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if(init) reset <= 5'h1f;
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else if((stage == STATE_FIRST) && (reset != 0))
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reset <= reset - 5'd1;
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end
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// ---------------------------------------------------------------------
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// ------------------ generate ram control signals ---------------------
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// ---------------------------------------------------------------------
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// all possible commands
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localparam CMD_INHIBIT = 4'b1111;
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localparam CMD_NOP = 4'b0111;
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localparam CMD_ACTIVE = 4'b0011;
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localparam CMD_READ = 4'b0101;
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localparam CMD_WRITE = 4'b0100;
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localparam CMD_BURST_TERMINATE = 4'b0110;
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localparam CMD_PRECHARGE = 4'b0010;
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localparam CMD_AUTO_REFRESH = 4'b0001;
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localparam CMD_LOAD_MODE = 4'b0000;
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reg [3:0] sd_cmd; // current command sent to sd ram
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// drive control signals according to current command
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assign sd_cs = sd_cmd[3];
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assign sd_ras = sd_cmd[2];
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assign sd_cas = sd_cmd[1];
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assign sd_we = sd_cmd[0];
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// drive ram data lines when writing, set them as inputs otherwise
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assign sd_data = mode[1] ? din_r : 16'bZZZZZZZZZZZZZZZZ;
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reg [1:0] mode;
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reg [15:0] din_r;
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reg [2:0] stage;
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always @(posedge clk) begin
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reg [12:0] addr_r;
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reg [1:0] ds_r;
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reg old_sync;
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if(|stage) stage <= stage + 1'd1;
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old_sync <= sync;
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if(~old_sync & sync) stage <= 1;
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sd_cmd <= CMD_INHIBIT; // default: idle
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if(reset != 0) begin
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// initialization takes place at the end of the reset phase
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if(stage == STATE_CMD_START) begin
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if(reset == 13) begin
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sd_cmd <= CMD_PRECHARGE;
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sd_addr[10] <= 1'b1; // precharge all banks
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end
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if(reset == 2) begin
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sd_cmd <= CMD_LOAD_MODE;
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sd_addr <= MODE;
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end
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end
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mode <= 0;
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sd_dqm <= 2'b11;
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end else begin
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// normal operation
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if(stage == STATE_CMD_START) begin
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if(we || oe) begin
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mode <= {we, oe};
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// RAS phase
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sd_cmd <= CMD_ACTIVE;
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sd_addr <= { 1'b0, addr[19:8] };
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sd_ba <= addr[21:20];
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ds_r <= ds;
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din_r <= din;
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addr_r <= { 4'b0010, addr[22], addr[7:0] }; // auto precharge
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end
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else begin
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sd_cmd <= CMD_AUTO_REFRESH;
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mode <= 0;
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end
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end
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// CAS phase
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if(stage == STATE_CMD_CONT && mode) begin
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sd_cmd <= mode[1] ? CMD_WRITE : CMD_READ;
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sd_addr <= addr_r;
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if(mode[1]) sd_dqm <= ~ds_r;
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else sd_dqm <= 2'b00;
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end
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if(stage == STATE_HIGHZ) begin
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sd_dqm <= 2'b11; // disable chip output
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mode[1] <= 0; // disable data output
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end
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if(stage == STATE_READ && mode) begin
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dout <= sd_data;
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end
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end
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end
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endmodule
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