396 lines
9.6 KiB
Systemverilog
396 lines
9.6 KiB
Systemverilog
//============================================================================
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//
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// HDMI Lite output module
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// Copyright (C) 2017 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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//============================================================================
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module hdmi_lite
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(
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input reset,
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input clk_video,
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input ce_pixel,
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input video_vs,
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input video_de,
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input [23:0] video_d,
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input clk_hdmi,
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input hdmi_hde,
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input hdmi_vde,
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output reg hdmi_de,
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output [23:0] hdmi_d,
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input [11:0] screen_w,
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input [11:0] screen_h,
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input quadbuf,
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// 0-3 => scale 1-4
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input [1:0] scale_x,
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input [1:0] scale_y,
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input scale_auto,
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input clk_vbuf,
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output [27:0] vbuf_address,
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input [127:0] vbuf_readdata,
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output [127:0] vbuf_writedata,
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output [7:0] vbuf_burstcount,
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output [15:0] vbuf_byteenable,
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input vbuf_waitrequest,
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input vbuf_readdatavalid,
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output reg vbuf_read,
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output reg vbuf_write
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);
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localparam [7:0] burstsz = 64;
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reg [1:0] nbuf = 0;
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wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
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wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
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assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress;
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assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
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wire [95:0] hf_out;
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wire [7:0] hf_usedw;
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reg hf_reset = 0;
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vbuf_fifo out_fifo
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(
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.aclr(hf_reset),
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.wrclk(clk_vbuf),
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.wrreq(vbuf_readdatavalid),
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.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
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.wrusedw(hf_usedw),
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.rdclk(~clk_hdmi),
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.rdreq(hf_rdreq),
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.q(hf_out)
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);
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reg [11:0] rd_stride;
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wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
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reg [27:0] vbuf_raddress;
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reg [7:0] vbuf_rburstcount;
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always @(posedge clk_vbuf) begin
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reg [18:0] rdcnt;
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reg [7:0] bcnt;
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reg vde1, vde2;
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reg [1:0] mcnt;
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reg [1:0] my;
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reg [18:0] fsz;
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reg [11:0] strd;
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vde1 <= hdmi_vde;
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vde2 <= vde1;
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if(vbuf_readdatavalid) begin
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rdcnt <= rdcnt + 1'd1;
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if(bcnt) bcnt <= bcnt - 1'd1;
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vbuf_raddress <= vbuf_raddress + 1'd1;
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end
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if(!bcnt && reading) reading <= 0;
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vbuf_read <= 0;
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if(~vbuf_waitrequest) begin
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if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
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vbuf_read <= 1;
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reading <= 1;
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bcnt <= rd_burst;
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vbuf_rburstcount <= rd_burst;
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rd_stride <= rd_stride - rd_burst;
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if(!(rd_stride - rd_burst)) rd_stride <= strd;
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if(!rdcnt) begin
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vbuf_raddress <= read_buf;
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mcnt <= my;
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end
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else if (rd_stride == strd) begin
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mcnt <= mcnt - 1'd1;
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if(!mcnt) mcnt <= my;
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else vbuf_raddress <= vbuf_raddress - strd;
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end
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end
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end
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hf_reset <= 0;
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if(vde2 & ~vde1) begin
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hf_reset <= 1;
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rdcnt <= 0;
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bcnt <= 0;
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rd_stride <= stride;
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strd <= stride;
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fsz <= framesz;
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my <= mult_y;
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end
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end
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reg [11:0] off_x, off_y;
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reg [11:0] x, y;
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reg [11:0] vh_height;
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reg [11:0] vh_width;
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reg [1:0] pcnt;
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reg [1:0] hload;
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wire hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
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wire de_in = hdmi_hde & hdmi_vde;
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always @(posedge clk_hdmi) begin
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reg [71:0] px_out;
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reg [1:0] mx;
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reg vde;
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vde <= hdmi_vde;
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if(vde & ~hdmi_vde) begin
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off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0;
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off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
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vh_height <= v_height;
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vh_width <= v_width;
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mx <= mult_x;
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end
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pcnt <= pcnt + 1'd1;
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if(pcnt == mx) begin
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pcnt <= 0;
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hload <= hload + 1'd1;
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end
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if(~de_in || x<off_x || y<off_y) begin
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hload <= 0;
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pcnt <= 0;
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end
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hdmi_de <= de_in;
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x <= x + 1'd1;
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if(~hdmi_de & de_in) x <= 0;
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if(hdmi_de & ~de_in) y <= y + 1'd1;
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if(~hdmi_vde) y <= 0;
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if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
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if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
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end
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//////////////////////////////////////////////////////////////////////////////
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reg reading = 0;
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reg writing = 0;
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reg op_split = 0;
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always @(posedge clk_vbuf) op_split <= ~op_split;
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wire allow_rd = ~reading & ~writing & op_split & ~reset;
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wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
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//////////////////////////////////////////////////////////////////////////////
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reg vf_rdreq = 0;
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wire [95:0] vf_out;
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assign vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
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vbuf_fifo in_fifo
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(
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.aclr(video_vs),
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.rdclk(clk_vbuf),
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.rdreq(vf_rdreq & ~vbuf_waitrequest),
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.q(vf_out),
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.wrclk(clk_video),
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.wrreq(infifo_wr),
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.data({video_de ? video_d : 24'd0, pix_acc})
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);
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assign vbuf_byteenable = '1;
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reg [35:0] addrque[3:0] = '{0,0,0,0};
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reg [7:0] flush_size;
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reg [27:0] flush_addr;
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reg flush_req = 0;
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reg flush_ack = 0;
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reg [27:0] vbuf_waddress;
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reg [7:0] vbuf_wburstcount;
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always @(posedge clk_vbuf) begin
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reg [7:0] ibcnt = 0;
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reg reqd = 0;
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reqd <= flush_req;
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if(~vbuf_waitrequest) begin
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vbuf_write <= vf_rdreq;
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if(~vf_rdreq && writing) writing <= 0;
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if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
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{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
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ibcnt <= addrque[0][7:0];
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addrque[0] <= addrque[1];
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addrque[1] <= addrque[2];
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addrque[2] <= addrque[3];
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addrque[3] <= 0;
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vf_rdreq <= 1;
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writing <= 1;
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end
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else if(flush_ack != reqd) begin
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if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
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else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
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else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
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else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
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flush_ack <= reqd;
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end
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if(vf_rdreq) begin
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if(ibcnt == 1) vf_rdreq <= 0;
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ibcnt <= ibcnt - 1'd1;
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end
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end
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end
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reg [11:0] stride;
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reg [18:0] framesz;
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reg [11:0] v_height;
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reg [11:0] v_width;
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reg [1:0] mult_x;
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reg [1:0] mult_y;
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reg [71:0] pix_acc;
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wire pix_wr = ce_pixel && video_de;
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reg [27:0] cur_addr;
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reg [11:0] video_x;
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reg [11:0] video_y;
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wire infifo_tail = ~video_de && video_x[1:0];
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wire infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
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wire [1:0] tm_y = (video_y > (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11;
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wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
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wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y;
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wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y;
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wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x;
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wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0);
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wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
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wire [23:0] t_fsz = l1_stride * t_height;
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reg [11:0] l1_width;
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reg [11:0] l1_stride;
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always @(posedge clk_video) begin
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reg [7:0] loaded = 0;
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reg [11:0] strd = 0;
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reg old_de = 0;
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reg old_vs = 0;
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old_vs <= video_vs;
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if(~old_vs & video_vs) begin
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cur_addr<= write_buf;
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video_x <= 0;
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video_y <= 0;
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loaded <= 0;
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strd <= 0;
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nbuf <= nbuf + 1'd1;
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stride <= l1_stride;
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framesz <= t_fsz[18:0];
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v_height<= t_height;
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v_width <= t_width;
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mult_x <= tmf_x;
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mult_y <= tmf_y;
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end
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if(pix_wr) begin
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case(video_x[1:0])
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0: pix_acc <= video_d; // zeroes upper bits too
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1: pix_acc[47:24] <= video_d;
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2: pix_acc[71:48] <= video_d;
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3: loaded <= loaded + 1'd1;
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endcase
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if(video_x<screen_w) video_x <= video_x + 1'd1;
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end
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old_de <= video_de;
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if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
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if(loaded + infifo_tail) begin
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flush_size <= loaded + infifo_tail;
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flush_addr <= cur_addr;
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flush_req <= ~flush_req;
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loaded <= 0;
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strd <= strd + loaded;
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end
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cur_addr <= cur_addr + loaded + infifo_tail;
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if(~video_de) begin
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if(video_y<screen_h) video_y <= video_y + 1'd1;
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video_x <= 0;
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strd <= 0;
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// measure width by first line (same as VIP)
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if(!video_y) begin
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l1_width <= video_x;
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l1_stride <= strd + loaded + infifo_tail;
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end
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end
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end
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end
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endmodule
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module vbuf_fifo
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(
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input aclr,
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input rdclk,
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input rdreq,
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output [95:0] q,
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input wrclk,
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input wrreq,
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input [95:0] data,
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output [7:0] wrusedw
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);
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dcfifo dcfifo_component
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(
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.aclr (aclr),
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.data (data),
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.rdclk (rdclk),
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.rdreq (rdreq),
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.wrclk (wrclk),
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.wrreq (wrreq),
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.q (q),
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.wrusedw (wrusedw),
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.eccstatus (),
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.rdempty (),
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.rdfull (),
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.rdusedw (),
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.wrempty (),
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.wrfull ()
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);
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defparam
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dcfifo_component.intended_device_family = "Cyclone V",
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dcfifo_component.lpm_numwords = 256,
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dcfifo_component.lpm_showahead = "OFF",
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dcfifo_component.lpm_type = "dcfifo",
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dcfifo_component.lpm_width = 96,
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dcfifo_component.lpm_widthu = 8,
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dcfifo_component.overflow_checking = "ON",
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dcfifo_component.rdsync_delaypipe = 5,
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dcfifo_component.read_aclr_synch = "OFF",
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dcfifo_component.underflow_checking = "ON",
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dcfifo_component.use_eab = "ON",
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dcfifo_component.write_aclr_synch = "OFF",
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dcfifo_component.wrsync_delaypipe = 5;
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endmodule
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