687 lines
16 KiB
Verilog
687 lines
16 KiB
Verilog
//
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// hps_io.v
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//
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// mist_io-like module for the Terasic DE10 board
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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// Copyright (c) 2017 Sorgelig (port to DE10-nano)
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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///////////////////////////////////////////////////////////////////////
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//
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// Use buffer to access SD card. It's time-critical part.
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//
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// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
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// clk_ps2 = CLK_SYS/(PS2DIV*2)
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//
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// WIDE=1 for 16 bit file I/O
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// VDNUM 1-4
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module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
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(
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input clk_sys,
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inout [44:0] HPS_BUS,
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// parameter STRLEN and the actual length of conf_str have to match
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input [(8*STRLEN)-1:0] conf_str,
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output reg [15:0] joystick_0,
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output reg [15:0] joystick_1,
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output reg [15:0] joystick_analog_0,
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output reg [15:0] joystick_analog_1,
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output [1:0] buttons,
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output forced_scandoubler,
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output reg [31:0] status,
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// SD config
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output reg [VD:0] img_mounted, // signaling that new image has been mounted
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output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted
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output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted
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// SD block level access
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input [31:0] sd_lba,
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input [VD:0] sd_rd, // only single sd_rd can be active at any given time
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input [VD:0] sd_wr, // only single sd_wr can be active at any given time
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output reg sd_ack,
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// do not use in new projects.
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// CID and CSD are fake except CSD image size field.
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input sd_conf,
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output reg sd_ack_conf,
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// SD byte level access. Signals for 2-PORT altsyncram.
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output reg [AW:0] sd_buff_addr,
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output reg [DW:0] sd_buff_dout,
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input [DW:0] sd_buff_din,
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output reg sd_buff_wr,
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// ARM -> FPGA download
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output reg ioctl_download = 0, // signal indicating an active download
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output reg [7:0] ioctl_index, // menu index used to upload the file
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output reg ioctl_wr,
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output reg [24:0] ioctl_addr, // in WIDE mode address will be incremented by 2
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output reg [DW:0] ioctl_dout,
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input ioctl_wait,
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// RTC MSM6242B layout
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output reg [64:0] RTC,
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// Seconds since 1970-01-01 00:00:00
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output reg [32:0] TIMESTAMP,
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// ps2 keyboard emulation
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output ps2_kbd_clk_out,
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output ps2_kbd_data_out,
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input ps2_kbd_clk_in,
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input ps2_kbd_data_in,
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input [2:0] ps2_kbd_led_status,
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input [2:0] ps2_kbd_led_use,
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output ps2_mouse_clk_out,
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output ps2_mouse_data_out,
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input ps2_mouse_clk_in,
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input ps2_mouse_data_in,
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// ps2 alternative interface.
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// [8] - extended, [9] - pressed, [10] - toggles with every press/release
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output reg [10:0] ps2_key = 0,
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// [24] - toggles with every event
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output reg [24:0] ps2_mouse = 0
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);
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localparam DW = (WIDE) ? 15 : 7;
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localparam AW = (WIDE) ? 7 : 8;
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localparam VD = VDNUM-1;
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wire io_wait = ioctl_wait;
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wire io_enable= |HPS_BUS[35:34];
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wire io_strobe= HPS_BUS[33];
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wire io_wide = (WIDE) ? 1'b1 : 1'b0;
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wire [15:0] io_din = HPS_BUS[31:16];
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reg [15:0] io_dout;
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assign HPS_BUS[37] = io_wait;
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assign HPS_BUS[36] = clk_sys;
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assign HPS_BUS[32] = io_wide;
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assign HPS_BUS[15:0] = io_dout;
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reg [7:0] cfg;
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assign buttons = cfg[1:0];
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//cfg[2] - vga_scaler handled in sys_top
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//cfg[3] - csync handled in sys_top
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assign forced_scandoubler = cfg[4];
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//cfg[5] - ypbpr handled in sys_top
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// command byte read by the io controller
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wire [15:0] sd_cmd =
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{
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2'b00,
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(VDNUM>=4) ? sd_wr[3] : 1'b0,
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(VDNUM>=3) ? sd_wr[2] : 1'b0,
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(VDNUM>=2) ? sd_wr[1] : 1'b0,
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(VDNUM>=4) ? sd_rd[3] : 1'b0,
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(VDNUM>=3) ? sd_rd[2] : 1'b0,
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(VDNUM>=2) ? sd_rd[1] : 1'b0,
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4'h5, sd_conf, 1'b1,
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sd_wr[0],
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sd_rd[0]
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};
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///////////////// calc video parameters //////////////////
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wire clk_100 = HPS_BUS[43];
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wire clk_vid = HPS_BUS[42];
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wire ce_pix = HPS_BUS[41];
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wire de = HPS_BUS[40];
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wire hs = HPS_BUS[39];
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wire vs = HPS_BUS[38];
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wire vs_hdmi = HPS_BUS[44];
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reg [31:0] vid_hcnt = 0;
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reg [31:0] vid_vcnt = 0;
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reg [7:0] vid_nres = 0;
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integer hcnt;
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always @(posedge clk_vid) begin
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integer vcnt;
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reg old_vs= 0, old_de = 0;
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reg calch = 0;
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if(ce_pix) begin
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old_vs <= vs;
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old_de <= de;
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if(~vs & ~old_de & de) vcnt <= vcnt + 1;
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if(calch & de) hcnt <= hcnt + 1;
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if(old_de & ~de) calch <= 0;
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if(old_vs & ~vs) begin
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if(hcnt && vcnt) begin
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if(vid_hcnt != hcnt || vid_vcnt != vcnt) vid_nres <= vid_nres + 1'd1;
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vid_hcnt <= hcnt;
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vid_vcnt <= vcnt;
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end
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vcnt <= 0;
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hcnt <= 0;
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calch <= 1;
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end
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end
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end
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reg [31:0] vid_htime = 0;
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reg [31:0] vid_vtime = 0;
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reg [31:0] vid_pix = 0;
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always @(posedge clk_100) begin
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integer vtime, htime, hcnt;
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reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
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reg calch = 0;
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old_vs <= vs;
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old_hs <= hs;
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old_vs2 <= old_vs;
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old_hs2 <= old_hs;
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vtime <= vtime + 1'd1;
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htime <= htime + 1'd1;
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if(~old_vs2 & old_vs) begin
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vid_pix <= hcnt;
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vid_vtime <= vtime;
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vtime <= 0;
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hcnt <= 0;
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end
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if(old_vs2 & ~old_vs) calch <= 1;
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if(~old_hs2 & old_hs) begin
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vid_htime <= htime;
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htime <= 0;
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end
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old_de <= de;
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old_de2 <= old_de;
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if(calch & old_de) hcnt <= hcnt + 1;
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if(old_de2 & ~old_de) calch <= 0;
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end
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reg [31:0] vid_vtime_hdmi;
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always @(posedge clk_100) begin
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integer vtime;
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reg old_vs, old_vs2;
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old_vs <= vs_hdmi;
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old_vs2 <= old_vs;
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vtime <= vtime + 1'd1;
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if(~old_vs2 & old_vs) begin
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vid_vtime_hdmi <= vtime;
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vtime <= 0;
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end
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end
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/////////////////////////////////////////////////////////
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reg [31:0] ps2_key_raw = 0;
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wire pressed = (ps2_key_raw[15:8] != 8'hf0);
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wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
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always@(posedge clk_sys) begin
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reg [15:0] cmd;
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reg [9:0] byte_cnt; // counts bytes
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reg [2:0] b_wr;
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reg [2:0] stick_idx;
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reg ps2skip = 0;
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sd_buff_wr <= b_wr[0];
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if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
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b_wr <= (b_wr<<1);
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{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
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if(~io_enable) begin
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if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
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if(cmd == 5 && !ps2skip) begin
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ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
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if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
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if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
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if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
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end
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if(cmd == 'h22) RTC[64] <= ~RTC[64];
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if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
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cmd <= 0;
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byte_cnt <= 0;
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sd_ack <= 0;
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sd_ack_conf <= 0;
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io_dout <= 0;
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ps2skip <= 0;
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end else begin
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if(io_strobe) begin
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io_dout <= 0;
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if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
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if(byte_cnt == 0) begin
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cmd <= io_din;
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case(io_din)
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'h19: sd_ack_conf <= 1;
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'h17,
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'h18: sd_ack <= 1;
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endcase
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sd_buff_addr <= 0;
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img_mounted <= 0;
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if(io_din == 5) ps2_key_raw <= 0;
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end else begin
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case(cmd)
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// buttons and switches
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'h01: cfg <= io_din[7:0];
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'h02: joystick_0 <= io_din;
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'h03: joystick_1 <= io_din;
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// store incoming ps2 mouse bytes
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'h04: begin
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mouse_data <= io_din[7:0];
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mouse_we <= 1;
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if(&io_din[15:8]) ps2skip <= 1;
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if(~&io_din[15:8] & ~ps2skip) begin
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case(byte_cnt)
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1: ps2_mouse[7:0] <= io_din[7:0];
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2: ps2_mouse[15:8] <= io_din[7:0];
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3: ps2_mouse[23:16] <= io_din[7:0];
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endcase
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end
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end
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// store incoming ps2 keyboard bytes
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'h05: begin
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if(&io_din[15:8]) ps2skip <= 1;
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if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
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kbd_data <= io_din[7:0];
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kbd_we <= 1;
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end
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// reading config string
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'h14: begin
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// returning a byte from string
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if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
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end
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// reading sd card status
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'h16: begin
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case(byte_cnt)
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1: io_dout <= sd_cmd;
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2: io_dout <= sd_lba[15:0];
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3: io_dout <= sd_lba[31:16];
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endcase
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end
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// send SD config IO -> FPGA
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// flag that download begins
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// sd card knows data is config if sd_dout_strobe is asserted
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// with sd_ack still being inactive (low)
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'h19,
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// send sector IO -> FPGA
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// flag that download begins
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'h17: begin
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sd_buff_dout <= io_din[DW:0];
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b_wr <= 1;
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end
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// reading sd card write data
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'h18: begin
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if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
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io_dout <= sd_buff_din;
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end
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// joystick analog
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'h1a: begin
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// first byte is joystick index
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if(byte_cnt == 1) stick_idx <= io_din[2:0];
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if(byte_cnt == 2) begin
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if(stick_idx == 0) joystick_analog_0 <= io_din;
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if(stick_idx == 1) joystick_analog_1 <= io_din;
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end
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end
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// notify image selection
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'h1c: begin
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img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
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img_readonly <= io_din[7];
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end
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// send image info
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'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
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// status, 32bit version
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'h1e: if(byte_cnt==1) status[15:0] <= io_din;
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else if(byte_cnt==2) status[31:16] <= io_din;
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// reading keyboard LED status
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'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
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// reading ps2 keyboard/mouse control
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'h21: begin
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if(byte_cnt == 1) begin
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io_dout <= kbd_data_host;
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kbd_rd <= 1;
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end
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if(byte_cnt == 2) begin
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io_dout <= mouse_data_host;
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mouse_rd <= 1;
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end
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end
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//RTC
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'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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//Video res.
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'h23: begin
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case(byte_cnt)
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1: io_dout <= vid_nres;
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2: io_dout <= vid_hcnt[15:0];
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3: io_dout <= vid_hcnt[31:16];
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4: io_dout <= vid_vcnt[15:0];
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5: io_dout <= vid_vcnt[31:16];
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6: io_dout <= vid_htime[15:0];
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7: io_dout <= vid_htime[31:16];
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8: io_dout <= vid_vtime[15:0];
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9: io_dout <= vid_vtime[31:16];
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10: io_dout <= vid_pix[15:0];
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11: io_dout <= vid_pix[31:16];
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12: io_dout <= vid_vtime_hdmi[15:0];
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13: io_dout <= vid_vtime_hdmi[31:16];
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endcase
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end
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//RTC
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'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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endcase
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end
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end
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end
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end
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/////////////////////////////// PS2 ///////////////////////////////
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reg clk_ps2;
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always @(negedge clk_sys) begin
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integer cnt;
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cnt <= cnt + 1'd1;
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if(cnt == PS2DIV) begin
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clk_ps2 <= ~clk_ps2;
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cnt <= 0;
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end
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end
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reg [7:0] kbd_data;
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reg kbd_we;
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wire [8:0] kbd_data_host;
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reg kbd_rd;
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ps2_device keyboard
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(
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.clk_sys(clk_sys),
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.wdata(kbd_data),
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.we(kbd_we),
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.ps2_clk(clk_ps2),
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.ps2_clk_out(ps2_kbd_clk_out),
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.ps2_dat_out(ps2_kbd_data_out),
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.ps2_clk_in(ps2_kbd_clk_in || !PS2WE),
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.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
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.rdata(kbd_data_host),
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.rd(kbd_rd)
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);
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reg [7:0] mouse_data;
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reg mouse_we;
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wire [8:0] mouse_data_host;
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reg mouse_rd;
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ps2_device mouse
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(
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.clk_sys(clk_sys),
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.wdata(mouse_data),
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.we(mouse_we),
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.ps2_clk(clk_ps2),
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.ps2_clk_out(ps2_mouse_clk_out),
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.ps2_dat_out(ps2_mouse_data_out),
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.ps2_clk_in(ps2_mouse_clk_in || !PS2WE),
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.ps2_dat_in(ps2_mouse_data_in || !PS2WE),
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.rdata(mouse_data_host),
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.rd(mouse_rd)
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);
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/////////////////////////////// DOWNLOADING ///////////////////////////////
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localparam UIO_FILE_TX = 8'h53;
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localparam UIO_FILE_TX_DAT = 8'h54;
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localparam UIO_FILE_INDEX = 8'h55;
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always@(posedge clk_sys) begin
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reg [15:0] cmd;
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reg has_cmd;
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reg [24:0] addr;
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reg wr;
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|
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ioctl_wr <= wr;
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wr <= 0;
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|
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if(~io_enable) has_cmd <= 0;
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else begin
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if(io_strobe) begin
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|
|
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if(!has_cmd) begin
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cmd <= io_din;
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has_cmd <= 1;
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end else begin
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|
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case(cmd)
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UIO_FILE_INDEX:
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begin
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ioctl_index <= io_din[7:0];
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end
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|
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UIO_FILE_TX:
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|
begin
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|
if(io_din[7:0]) begin
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|
addr <= 0;
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ioctl_download <= 1;
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end else begin
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|
ioctl_addr <= addr;
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ioctl_download <= 0;
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|
end
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|
end
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|
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UIO_FILE_TX_DAT:
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|
begin
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ioctl_addr <= addr;
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ioctl_dout <= io_din[DW:0];
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wr <= 1;
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addr <= addr + (WIDE ? 2'd2 : 2'd1);
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end
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endcase
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end
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end
|
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end
|
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end
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|
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endmodule
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|
|
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//////////////////////////////////////////////////////////////////////////////////
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|
|
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module ps2_device #(parameter PS2_FIFO_BITS=5)
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(
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input clk_sys,
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|
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input [7:0] wdata,
|
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input we,
|
|
|
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input ps2_clk,
|
|
output reg ps2_clk_out,
|
|
output reg ps2_dat_out,
|
|
output reg tx_empty,
|
|
|
|
input ps2_clk_in,
|
|
input ps2_dat_in,
|
|
|
|
output [8:0] rdata,
|
|
input rd
|
|
);
|
|
|
|
|
|
(* ramstyle = "logic" *) reg [7:0] fifo[1<<PS2_FIFO_BITS];
|
|
|
|
reg [PS2_FIFO_BITS-1:0] wptr;
|
|
reg [PS2_FIFO_BITS-1:0] rptr;
|
|
|
|
reg [2:0] rx_state = 0;
|
|
reg [3:0] tx_state = 0;
|
|
|
|
reg has_data;
|
|
reg [7:0] data;
|
|
assign rdata = {has_data, data};
|
|
|
|
always@(posedge clk_sys) begin
|
|
reg [7:0] tx_byte;
|
|
reg parity;
|
|
reg r_inc;
|
|
reg old_clk;
|
|
reg [1:0] timeout;
|
|
|
|
reg [3:0] rx_cnt;
|
|
|
|
reg c1,c2,d1;
|
|
|
|
tx_empty <= ((wptr == rptr) && (tx_state == 0));
|
|
|
|
if(we) begin
|
|
fifo[wptr] <= wdata;
|
|
wptr <= wptr + 1'd1;
|
|
end
|
|
|
|
if(rd) has_data <= 0;
|
|
|
|
c1 <= ps2_clk_in;
|
|
c2 <= c1;
|
|
d1 <= ps2_dat_in;
|
|
if(!rx_state && !tx_state && ~c2 && c1 && ~d1) begin
|
|
rx_state <= rx_state + 1'b1;
|
|
ps2_dat_out <= 1;
|
|
end
|
|
|
|
old_clk <= ps2_clk;
|
|
if(~old_clk & ps2_clk) begin
|
|
|
|
if(rx_state) begin
|
|
case(rx_state)
|
|
1: begin
|
|
rx_state <= rx_state + 1'b1;
|
|
rx_cnt <= 0;
|
|
end
|
|
|
|
2: begin
|
|
if(rx_cnt <= 7) data <= {d1, data[7:1]};
|
|
else rx_state <= rx_state + 1'b1;
|
|
rx_cnt <= rx_cnt + 1'b1;
|
|
end
|
|
|
|
3: if(d1) begin
|
|
rx_state <= rx_state + 1'b1;
|
|
ps2_dat_out <= 0;
|
|
end
|
|
|
|
4: begin
|
|
ps2_dat_out <= 1;
|
|
has_data <= 1;
|
|
rx_state <= 0;
|
|
end
|
|
endcase
|
|
end else begin
|
|
|
|
// transmitter is idle?
|
|
if(tx_state == 0) begin
|
|
// data in fifo present?
|
|
if(c2 && c1 && d1 && wptr != rptr) begin
|
|
|
|
timeout <= timeout - 1'd1;
|
|
if(!timeout) begin
|
|
tx_byte <= fifo[rptr];
|
|
rptr <= rptr + 1'd1;
|
|
|
|
// reset parity
|
|
parity <= 1;
|
|
|
|
// start transmitter
|
|
tx_state <= 1;
|
|
|
|
// put start bit on data line
|
|
ps2_dat_out <= 0; // start bit is 0
|
|
end
|
|
end
|
|
end else begin
|
|
|
|
// transmission of 8 data bits
|
|
if((tx_state >= 1)&&(tx_state < 9)) begin
|
|
ps2_dat_out <= tx_byte[0]; // data bits
|
|
tx_byte[6:0] <= tx_byte[7:1]; // shift down
|
|
if(tx_byte[0])
|
|
parity <= !parity;
|
|
end
|
|
|
|
// transmission of parity
|
|
if(tx_state == 9) ps2_dat_out <= parity;
|
|
|
|
// transmission of stop bit
|
|
if(tx_state == 10) ps2_dat_out <= 1; // stop bit is 1
|
|
|
|
// advance state machine
|
|
if(tx_state < 11) tx_state <= tx_state + 1'd1;
|
|
else tx_state <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
if(~old_clk & ps2_clk) ps2_clk_out <= 1;
|
|
if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2));
|
|
|
|
end
|
|
|
|
endmodule
|