70 lines
1.3 KiB
Verilog
70 lines
1.3 KiB
Verilog
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module i2c
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(
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input CLK,
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input START,
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input [23:0] I2C_DATA,
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output reg END = 1,
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output reg ACK = 0,
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//I2C bus
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output I2C_SCL,
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inout I2C_SDA
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);
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// Clock Setting
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parameter CLK_Freq = 50_000_000; // 50 MHz
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parameter I2C_Freq = 400_000; // 400 KHz
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reg I2C_CLOCK;
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always@(negedge CLK) begin
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integer mI2C_CLK_DIV = 0;
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if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin
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mI2C_CLK_DIV <= mI2C_CLK_DIV + 1;
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end else begin
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mI2C_CLK_DIV <= 0;
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I2C_CLOCK <= ~I2C_CLOCK;
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end
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end
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assign I2C_SCL = SCLK | I2C_CLOCK;
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assign I2C_SDA = SDO ? 1'bz : 1'b0;
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reg SCLK = 1, SDO = 1;
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always @(posedge CLK) begin
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reg old_clk;
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reg old_st;
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reg [5:0] SD_COUNTER = 'b111111;
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reg [0:31] SD;
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old_clk <= I2C_CLOCK;
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old_st <= START;
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if(~old_st && START) begin
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SCLK <= 1;
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SDO <= 1;
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ACK <= 0;
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END <= 0;
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SD <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011};
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SD_COUNTER <= 0;
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end else begin
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if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
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SD_COUNTER <= SD_COUNTER + 6'd1;
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case(SD_COUNTER)
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01: SCLK <= 0;
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10,19,28: ACK <= ACK | I2C_SDA;
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29: SCLK <= 1;
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32: END <= 1;
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endcase
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end
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if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]];
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end
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end
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endmodule
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