53 lines
1.8 KiB
Verilog
53 lines
1.8 KiB
Verilog
// in_split.v
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`timescale 1 ps / 1 ps
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module in_split (
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input wire clk, // input.clk
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input wire ce, // .ce
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input wire de, // .de
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input wire h_sync, // .h_sync
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input wire v_sync, // .v_sync
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input wire f, // .f
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input wire [23:0] data, // .data
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output wire vid_clk, // Output.vid_clk
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output reg vid_datavalid, // .vid_datavalid
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output reg [1:0] vid_de, // .vid_de
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output reg [1:0] vid_f, // .vid_f
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output reg [1:0] vid_h_sync, // .vid_h_sync
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output reg [1:0] vid_v_sync, // .vid_v_sync
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output reg [47:0] vid_data, // .vid_data
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output wire vid_locked, // .vid_locked
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output wire [7:0] vid_color_encoding, // .vid_color_encoding
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output wire [7:0] vid_bit_width, // .vid_bit_width
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input wire clipping, // .clipping
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input wire overflow, // .overflow
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input wire sof, // .sof
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input wire sof_locked, // .sof_locked
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input wire refclk_div, // .refclk_div
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input wire padding // .padding
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);
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assign vid_bit_width = 0;
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assign vid_color_encoding = 0;
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assign vid_locked = 1;
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assign vid_clk = clk;
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always @(posedge clk) begin
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reg odd = 0;
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vid_datavalid <= 0;
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if(ce) begin
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vid_de[odd] <= de;
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vid_f[odd] <= f;
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vid_h_sync[odd] <= h_sync;
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vid_v_sync[odd] <= v_sync;
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if(odd) vid_data[47:24] <= data;
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else vid_data[23:0] <= data;
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odd <= ~odd;
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vid_datavalid <= odd;
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end
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end
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endmodule
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