51 lines
1.4 KiB
Verilog
51 lines
1.4 KiB
Verilog
// reset_source.v
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// This file was auto-generated as a prototype implementation of a module
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// created in component editor. It ties off all outputs to ground and
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// ignores all inputs. It needs to be edited to make it do something
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// useful.
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//
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// This file will not be automatically regenerated. You should check it in
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// to your version control system if you want to keep it.
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`timescale 1 ps / 1 ps
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module reset_source
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(
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input wire clk, // clock.clk
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input wire reset_hps, // reset_hps.reset
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output wire reset_sys, // reset_sys.reset
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output wire reset_cold, // reset_cold.reset
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input wire cold_req, // reset_ctl.cold_req
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output wire reset, // .reset
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input wire reset_req, // .reset_req
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input wire reset_vip, // .reset_vip
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input wire warm_req, // .warm_req
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output wire reset_warm // reset_warm.reset
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);
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assign reset_cold = cold_req;
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assign reset_warm = warm_req;
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wire reset_m = sys_reset | reset_hps | reset_req;
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assign reset = reset_m;
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assign reset_sys = reset_m | reset_vip;
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reg sys_reset = 1;
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always @(posedge clk) begin
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integer timeout = 0;
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reg reset_lock = 0;
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reset_lock <= reset_lock | cold_req;
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if(timeout < 2000000) begin
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sys_reset <= 1;
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timeout <= timeout + 1;
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reset_lock <= 0;
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end
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else begin
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sys_reset <= reset_lock;
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end
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end
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endmodule
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