87 lines
4.6 KiB
Verilog
87 lines
4.6 KiB
Verilog
// megafunction wizard: %Altera PLL Reconfig v17.0%
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// GENERATION: XML
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// pll_hdmi_cfg.v
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// Generated using ACDS version 17.0 598
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`timescale 1 ps / 1 ps
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module pll_hdmi_cfg #(
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parameter ENABLE_BYTEENABLE = 0,
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parameter BYTEENABLE_WIDTH = 4,
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parameter RECONFIG_ADDR_WIDTH = 6,
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parameter RECONFIG_DATA_WIDTH = 32,
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parameter reconf_width = 64,
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parameter WAIT_FOR_LOCK = 1
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) (
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input wire mgmt_clk, // mgmt_clk.clk
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input wire mgmt_reset, // mgmt_reset.reset
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output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
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input wire mgmt_read, // .read
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input wire mgmt_write, // .write
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output wire [31:0] mgmt_readdata, // .readdata
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input wire [5:0] mgmt_address, // .address
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input wire [31:0] mgmt_writedata, // .writedata
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output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
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input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
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);
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altera_pll_reconfig_top #(
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.device_family ("Cyclone V"),
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.ENABLE_MIF (0),
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.MIF_FILE_NAME ("sys/pll_hdmi_cfg.mif"),
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.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
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.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
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.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
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.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
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.reconf_width (reconf_width),
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.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
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) pll_hdmi_cfg_inst (
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.mgmt_clk (mgmt_clk), // mgmt_clk.clk
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.mgmt_reset (mgmt_reset), // mgmt_reset.reset
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.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
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.mgmt_read (mgmt_read), // .read
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.mgmt_write (mgmt_write), // .write
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.mgmt_readdata (mgmt_readdata), // .readdata
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.mgmt_address (mgmt_address), // .address
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.mgmt_writedata (mgmt_writedata), // .writedata
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.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
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.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
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.mgmt_byteenable (4'b0000) // (terminated)
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);
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endmodule
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// Retrieval info: <?xml version="1.0"?>
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//<!--
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// Generated by Altera MegaWizard Launcher Utility version 1.0
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// ************************************************************
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// Copyright (C) 1991-2018 Altera Corporation
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// Any megafunction design, and related net list (encrypted or decrypted),
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// support information, device programming or simulation file, and any other
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// associated documentation or information provided by Altera or a partner
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// under Altera's Megafunction Partnership Program may be used only to
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// program PLD devices (but not masked PLD devices) from Altera. Any other
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// use of such megafunction design, net list, support information, device
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// programming or simulation file, or any other related documentation or
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// information is prohibited for any other purpose, including, but not
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// limited to modification, reverse engineering, de-compiling, or use with
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// any other silicon devices, unless such use is explicitly licensed under
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// a separate agreement with Altera or a megafunction partner. Title to
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// the intellectual property, including patents, copyrights, trademarks,
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// trade secrets, or maskworks, embodied in any such megafunction design,
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// net list, support information, device programming or simulation file, or
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// any other related documentation or information provided by Altera or a
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// megafunction partner, remains with Altera, the megafunction partner, or
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// their respective licensors. No other licenses, including any licenses
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// needed under any third party's intellectual property, are provided herein.
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//-->
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// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
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// Retrieval info: <generic name="device_family" value="Cyclone V" />
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// Retrieval info: <generic name="ENABLE_MIF" value="false" />
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// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_hdmi_cfg.mif" />
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// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
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// Retrieval info: </instance>
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// IPFS_FILES : pll_hdmi_cfg.vo
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// RELATED_FILES: pll_hdmi_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
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