429 lines
14 KiB
Verilog
429 lines
14 KiB
Verilog
// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1ps/1ps
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module altera_pll_reconfig_top
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#(
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parameter reconf_width = 64,
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parameter device_family = "Stratix V",
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parameter RECONFIG_ADDR_WIDTH = 6,
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parameter RECONFIG_DATA_WIDTH = 32,
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parameter ROM_ADDR_WIDTH = 9,
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parameter ROM_DATA_WIDTH = 32,
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parameter ROM_NUM_WORDS = 512,
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parameter ENABLE_MIF = 0,
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parameter MIF_FILE_NAME = "",
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parameter ENABLE_BYTEENABLE = 0,
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parameter BYTEENABLE_WIDTH = 4,
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parameter WAIT_FOR_LOCK = 1
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) (
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//input
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input wire mgmt_clk,
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input wire mgmt_reset,
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//conduits
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output wire [reconf_width-1:0] reconfig_to_pll,
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input wire [reconf_width-1:0] reconfig_from_pll,
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// user data (avalon-MM slave interface)
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output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
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output wire mgmt_waitrequest,
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input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address,
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input wire mgmt_read,
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input wire mgmt_write,
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input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
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//conditional input
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input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
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);
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localparam NM28_START_REG = 6'b000010;
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localparam NM20_START_REG = 9'b000000000;
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localparam NM20_MIFSTART_ADDR = 9'b000010000;
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localparam MIF_STATE_DONE = 2'b00;
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localparam MIF_STATE_START = 2'b01;
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localparam MIF_STATE_BUSY = 2'b10;
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wire mgmt_byteenable_write;
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assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ?
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((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) :
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mgmt_write;
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generate
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if (device_family == "Arria 10")
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begin:nm20_reconfig
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if(ENABLE_MIF == 1)
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begin:mif_reconfig_20nm // Generate Reconfig with MIF
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// MIF-related regs/wires
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reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
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reg reconfig_mgmt_read;
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reg reconfig_mgmt_write;
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reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
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wire reconfig_mgmt_waitrequest;
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wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
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wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
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wire mif_busy;
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wire mif2reconfig_read;
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wire mif2reconfig_write;
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wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
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wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
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reg mif_select;
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//wire mif_user_start; // start signal provided by user to start mif
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//reg user_start;
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reg [1:0] mif_curstate;
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reg [1:0] mif_nextstate;
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wire mif_start; //start signal to mif reader
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assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
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// Don't output readdata if MIF streaming is taking place
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assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
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//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
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assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
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//mif base addr is initially specified by the user
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assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
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//MIF statemachine
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always @(posedge mgmt_clk)
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begin
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if(mgmt_reset)
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mif_curstate <= MIF_STATE_DONE;
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else
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mif_curstate <= mif_nextstate;
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end
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always @(*)
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begin
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case (mif_curstate)
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MIF_STATE_DONE:
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begin
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if(mif_start)
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mif_nextstate <= MIF_STATE_START;
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else
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mif_nextstate <= MIF_STATE_DONE;
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end
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MIF_STATE_START:
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begin
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mif_nextstate <= MIF_STATE_BUSY;
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end
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MIF_STATE_BUSY:
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begin
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if(mif_busy)
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mif_nextstate <= MIF_STATE_BUSY;
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else
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mif_nextstate <= MIF_STATE_DONE;
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end
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endcase
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end
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//Mif muxes
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always @(*)
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begin
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if (mgmt_reset)
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begin
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reconfig_mgmt_addr <= 0;
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reconfig_mgmt_read <= 0;
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reconfig_mgmt_write <= 0;
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reconfig_mgmt_writedata <= 0;
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//user_start <= 0;
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end
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else
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begin
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reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
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reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
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reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
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reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
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//user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
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end
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end
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always @(*)
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begin
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if (mgmt_reset)
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begin
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mif_select <= 0;
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end
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else
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begin
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mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
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end
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end
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twentynm_pll_reconfig_mif_reader
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#(
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.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
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.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
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.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
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.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
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.ROM_NUM_WORDS(ROM_NUM_WORDS),
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.DEVICE_FAMILY(device_family),
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.ENABLE_MIF(ENABLE_MIF),
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.MIF_FILE_NAME(MIF_FILE_NAME)
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) twentynm_pll_reconfig_mif_reader_inst0 (
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.mif_clk(mgmt_clk),
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.mif_rst(mgmt_reset),
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//Altera_PLL Reconfig interface
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//inputs
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.reconfig_waitrequest(reconfig_mgmt_waitrequest),
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//.reconfig_read_data(reconfig_mgmt_readdata),
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//outputs
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.reconfig_write_data(mif2reconfig_writedata),
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.reconfig_addr(mif2reconfig_addr),
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.reconfig_write(mif2reconfig_write),
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.reconfig_read(mif2reconfig_read),
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//MIF Ctrl Interface
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//inputs
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.mif_base_addr(mif_base_addr),
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.mif_start(mif_start),
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//outputs
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.mif_busy(mif_busy)
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);
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// ------ END MIF-RELATED MANAGEMENT ------
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twentynm_iopll_reconfig_core
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#(
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.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
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) twentynm_iopll_reconfig_core_inst (
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// Inputs
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.mgmt_clk(mgmt_clk),
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.mgmt_rst_n(~mgmt_reset),
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.mgmt_read(reconfig_mgmt_read),
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.mgmt_write(reconfig_mgmt_write),
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.mgmt_address(reconfig_mgmt_addr),
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.mgmt_writedata(reconfig_mgmt_writedata),
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// Outputs
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.mgmt_readdata(reconfig_mgmt_readdata),
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.mgmt_waitrequest(reconfig_mgmt_waitrequest),
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// PLL Conduits
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.reconfig_to_pll(reconfig_to_pll),
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.reconfig_from_pll(reconfig_from_pll)
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);
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end // End generate reconfig with MIF
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else
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begin:reconfig_core_20nm
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twentynm_iopll_reconfig_core
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#(
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.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
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) twentynm_iopll_reconfig_core_inst (
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// Inputs
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.mgmt_clk(mgmt_clk),
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.mgmt_rst_n(~mgmt_reset),
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.mgmt_read(mgmt_read),
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.mgmt_write(mgmt_byteenable_write),
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.mgmt_address(mgmt_address),
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.mgmt_writedata(mgmt_writedata),
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// Outputs
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.mgmt_readdata(mgmt_readdata),
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.mgmt_waitrequest(mgmt_waitrequest),
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// PLL Conduits
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.reconfig_to_pll(reconfig_to_pll),
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.reconfig_from_pll(reconfig_from_pll)
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);
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end
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end // 20nm reconfig
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else
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begin:NM28_reconfig
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if (ENABLE_MIF == 1)
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begin:mif_reconfig // Generate Reconfig with MIF
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// MIF-related regs/wires
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reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
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reg reconfig_mgmt_read;
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reg reconfig_mgmt_write;
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reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
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wire reconfig_mgmt_waitrequest;
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wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
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wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
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wire mif2reconfig_busy;
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wire mif2reconfig_read;
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wire mif2reconfig_write;
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wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
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wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
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reg mif_select;
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reg user_start;
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wire reconfig2mif_start_out;
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assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
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// Don't output readdata if MIF streaming is taking place
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assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
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always @(posedge mgmt_clk)
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begin
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if (mgmt_reset)
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begin
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reconfig_mgmt_addr <= 0;
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reconfig_mgmt_read <= 0;
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reconfig_mgmt_write <= 0;
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reconfig_mgmt_writedata <= 0;
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user_start <= 0;
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end
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else
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begin
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reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
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reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
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reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
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reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
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user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
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end
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end
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always @(*)
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begin
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if (mgmt_reset)
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begin
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mif_select <= 0;
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end
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else
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begin
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mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
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end
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end
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altera_pll_reconfig_mif_reader
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#(
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.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
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.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
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.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
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.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
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.ROM_NUM_WORDS(ROM_NUM_WORDS),
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.DEVICE_FAMILY(device_family),
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.ENABLE_MIF(ENABLE_MIF),
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.MIF_FILE_NAME(MIF_FILE_NAME)
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) altera_pll_reconfig_mif_reader_inst0 (
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.mif_clk(mgmt_clk),
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.mif_rst(mgmt_reset),
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//Altera_PLL Reconfig interface
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//inputs
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.reconfig_busy(reconfig_mgmt_waitrequest),
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.reconfig_read_data(reconfig_mgmt_readdata),
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//outputs
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.reconfig_write_data(mif2reconfig_writedata),
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.reconfig_addr(mif2reconfig_addr),
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.reconfig_write(mif2reconfig_write),
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.reconfig_read(mif2reconfig_read),
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//MIF Ctrl Interface
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//inputs
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.mif_base_addr(mif_base_addr),
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.mif_start(reconfig2mif_start_out),
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//outputs
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.mif_busy(mif2reconfig_busy)
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);
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// ------ END MIF-RELATED MANAGEMENT ------
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altera_pll_reconfig_core
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#(
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.reconf_width(reconf_width),
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.device_family(device_family),
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.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
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.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
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.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
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.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
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.ROM_NUM_WORDS(ROM_NUM_WORDS)
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) altera_pll_reconfig_core_inst0 (
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//inputs
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.mgmt_clk(mgmt_clk),
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.mgmt_reset(mgmt_reset),
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//PLL interface conduits
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.reconfig_to_pll(reconfig_to_pll),
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.reconfig_from_pll(reconfig_from_pll),
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//User data outputs
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.mgmt_readdata(reconfig_mgmt_readdata),
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.mgmt_waitrequest(reconfig_mgmt_waitrequest),
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//User data inputs
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.mgmt_address(reconfig_mgmt_addr),
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.mgmt_read(reconfig_mgmt_read),
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.mgmt_write(reconfig_mgmt_write),
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.mgmt_writedata(reconfig_mgmt_writedata),
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// other
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.mif_start_out(reconfig2mif_start_out),
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.mif_base_addr(mif_base_addr)
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);
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end // End generate reconfig with MIF
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else
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begin:reconfig_core // Generate Reconfig core only
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wire reconfig2mif_start_out;
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wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
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altera_pll_reconfig_core
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#(
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.reconf_width(reconf_width),
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.device_family(device_family),
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.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
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.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
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.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
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.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
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.ROM_NUM_WORDS(ROM_NUM_WORDS)
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) altera_pll_reconfig_core_inst0 (
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//inputs
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.mgmt_clk(mgmt_clk),
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.mgmt_reset(mgmt_reset),
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//PLL interface conduits
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.reconfig_to_pll(reconfig_to_pll),
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.reconfig_from_pll(reconfig_from_pll),
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//User data outputs
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.mgmt_readdata(mgmt_readdata),
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.mgmt_waitrequest(mgmt_waitrequest),
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//User data inputs
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.mgmt_address(mgmt_address),
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.mgmt_read(mgmt_read),
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.mgmt_write(mgmt_byteenable_write),
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.mgmt_writedata(mgmt_writedata),
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// other
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.mif_start_out(reconfig2mif_start_out),
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.mif_base_addr(mif_base_addr)
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);
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end // End generate reconfig core only
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end // End 28nm Reconfig
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endgenerate
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endmodule
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