427 lines
10 KiB
Verilog
427 lines
10 KiB
Verilog
//-----------------------------------------------------------------
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// SPDIF Transmitter
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// V0.1
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// Ultra-Embedded.com
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// Copyright 2012
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//
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// Email: admin@ultra-embedded.com
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//
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// License: GPL
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// If you would like a version with a more permissive license for
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// use in closed source commercial applications please contact me
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// for details.
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//-----------------------------------------------------------------
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//
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// This file is open source HDL; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as
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// published by the Free Software Foundation; either version 2 of
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// the License, or (at your option) any later version.
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//
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// This file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this file; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//-----------------------------------------------------------------
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// altera message_off 10762
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// altera message_off 10240
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module spdif
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//-----------------------------------------------------------------
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// Params
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//-----------------------------------------------------------------
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#(
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parameter CLK_RATE = 50000000,
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parameter AUDIO_RATE = 48000,
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// Generated params
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parameter WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*128),
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parameter ERROR_BASE = 10000,
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parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
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)
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//-----------------------------------------------------------------
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// Ports
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//-----------------------------------------------------------------
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(
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input clk_i,
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input rst_i,
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input half_rate,
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// Output
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output spdif_o,
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// Audio interface (16-bit x 2 = RL)
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input [15:0] audio_r,
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input [15:0] audio_l,
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output sample_req_o
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);
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reg lpf_ce;
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always @(negedge clk_i) begin
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reg [3:0] div;
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div <= div + 1'd1;
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if(div == 13) div <= 0;
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lpf_ce <= !div;
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end
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wire [15:0] al, ar;
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lpf48k #(15) lpf_l
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(
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.RESET(rst_i),
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.CLK(clk_i),
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.CE(lpf_ce),
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.ENABLE(1),
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.IDATA(audio_l),
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.ODATA(al)
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);
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lpf48k #(15) lpf_r
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(
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.RESET(rst_i),
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.CLK(clk_i),
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.CE(lpf_ce),
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.ENABLE(1),
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.IDATA(audio_r),
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.ODATA(ar)
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);
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reg bit_clk_q;
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// Clock pulse generator
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always @ (posedge rst_i or posedge clk_i) begin
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reg [31:0] count_q;
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reg [31:0] error_q;
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reg ce;
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if (rst_i) begin
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count_q <= 0;
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error_q <= 0;
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bit_clk_q <= 1;
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ce <= 0;
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end
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else
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begin
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if(count_q == WHOLE_CYCLES-1) begin
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if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
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error_q <= error_q + ERRORS_PER_BIT[31:0];
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count_q <= 0;
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end else begin
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error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
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count_q <= count_q + 1;
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end
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end else if(count_q == WHOLE_CYCLES) begin
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count_q <= 0;
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end else begin
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count_q <= count_q + 1;
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end
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bit_clk_q <= 0;
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if(!count_q) begin
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ce <= ~ce;
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if(~half_rate || ce) bit_clk_q <= 1;
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end
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end
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end
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//-----------------------------------------------------------------
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// Core SPDIF
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//-----------------------------------------------------------------
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wire [31:0] sample_i = {ar, al};
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spdif_core
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u_core
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(
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.clk_i(clk_i),
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.rst_i(rst_i),
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.bit_out_en_i(bit_clk_q),
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.spdif_o(spdif_o),
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.sample_i(sample_i),
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.sample_req_o(sample_req_o)
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);
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endmodule
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module spdif_core
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(
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input clk_i,
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input rst_i,
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// SPDIF bit output enable
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// Single cycle pulse synchronous to clk_i which drives
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// the output bit rate.
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// For 44.1KHz, 44100×32×2×2 = 5,644,800Hz
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// For 48KHz, 48000×32×2×2 = 6,144,000Hz
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input bit_out_en_i,
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// Output
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output spdif_o,
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// Audio interface (16-bit x 2 = RL)
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input [31:0] sample_i,
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output reg sample_req_o
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);
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//-----------------------------------------------------------------
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// Registers
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//-----------------------------------------------------------------
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reg [15:0] audio_sample_q;
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reg [8:0] subframe_count_q;
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reg load_subframe_q;
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reg [7:0] preamble_q;
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wire [31:0] subframe_w;
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reg [5:0] bit_count_q;
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reg bit_toggle_q;
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reg spdif_out_q;
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reg [5:0] parity_count_q;
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//-----------------------------------------------------------------
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// Subframe Counter
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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begin
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if (rst_i == 1'b1)
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subframe_count_q <= 9'd0;
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else if (load_subframe_q)
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begin
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// 192 frames (384 subframes) in an audio block
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if (subframe_count_q == 9'd383)
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subframe_count_q <= 9'd0;
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else
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subframe_count_q <= subframe_count_q + 9'd1;
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end
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end
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//-----------------------------------------------------------------
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// Sample capture
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//-----------------------------------------------------------------
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reg [15:0] sample_buf_q;
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always @ (posedge rst_i or posedge clk_i )
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begin
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if (rst_i == 1'b1)
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begin
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audio_sample_q <= 16'h0000;
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sample_buf_q <= 16'h0000;
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sample_req_o <= 1'b0;
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end
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else if (load_subframe_q)
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begin
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// Start of frame (first subframe)?
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if (subframe_count_q[0] == 1'b0)
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begin
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// Use left sample
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audio_sample_q <= sample_i[15:0];
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// Store right sample
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sample_buf_q <= sample_i[31:16];
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// Request next sample
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sample_req_o <= 1'b1;
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end
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else
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begin
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// Use right sample
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audio_sample_q <= sample_buf_q;
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sample_req_o <= 1'b0;
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end
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end
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else
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sample_req_o <= 1'b0;
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end
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// Timeslots 3 - 0 = Preamble
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assign subframe_w[3:0] = 4'b0000;
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// Timeslots 7 - 4 = 24-bit audio LSB
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assign subframe_w[7:4] = 4'b0000;
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// Timeslots 11 - 8 = 20-bit audio LSB
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assign subframe_w[11:8] = 4'b0000;
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// Timeslots 27 - 12 = 16-bit audio
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assign subframe_w[27:12] = audio_sample_q;
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// Timeslots 28 = Validity
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assign subframe_w[28] = 1'b0; // Valid
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// Timeslots 29 = User bit
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assign subframe_w[29] = 1'b0;
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// Timeslots 30 = Channel status bit
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assign subframe_w[30] = 1'b0;
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// Timeslots 31 = Even Parity bit (31:4)
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assign subframe_w[31] = 1'b0;
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//-----------------------------------------------------------------
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// Preamble
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//-----------------------------------------------------------------
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localparam PREAMBLE_Z = 8'b00010111;
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localparam PREAMBLE_Y = 8'b00100111;
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localparam PREAMBLE_X = 8'b01000111;
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reg [7:0] preamble_r;
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always @ *
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begin
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// Start of audio block?
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// Z(B) - Left channel
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if (subframe_count_q == 9'd0)
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preamble_r = PREAMBLE_Z; // Z(B)
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// Right Channel?
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else if (subframe_count_q[0] == 1'b1)
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preamble_r = PREAMBLE_Y; // Y(W)
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// Left Channel (but not start of block)?
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else
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preamble_r = PREAMBLE_X; // X(M)
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end
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always @ (posedge rst_i or posedge clk_i )
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if (rst_i == 1'b1)
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preamble_q <= 8'h00;
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else if (load_subframe_q)
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preamble_q <= preamble_r;
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//-----------------------------------------------------------------
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// Parity Counter
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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begin
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if (rst_i == 1'b1)
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begin
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parity_count_q <= 6'd0;
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end
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// Time to output a bit?
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else if (bit_out_en_i)
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begin
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// Preamble bits?
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if (bit_count_q < 6'd8)
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begin
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parity_count_q <= 6'd0;
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end
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// Normal timeslots
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else if (bit_count_q < 6'd62)
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begin
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// On first pass through this timeslot, count number of high bits
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if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
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parity_count_q <= parity_count_q + 6'd1;
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end
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end
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end
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//-----------------------------------------------------------------
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// Bit Counter
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i)
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begin
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if (rst_i == 1'b1)
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begin
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bit_count_q <= 6'b0;
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load_subframe_q <= 1'b1;
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end
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// Time to output a bit?
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else if (bit_out_en_i)
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begin
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// 32 timeslots (x2 for double frequency)
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if (bit_count_q == 6'd63)
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begin
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bit_count_q <= 6'd0;
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load_subframe_q <= 1'b1;
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end
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else
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begin
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bit_count_q <= bit_count_q + 6'd1;
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load_subframe_q <= 1'b0;
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end
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end
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else
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load_subframe_q <= 1'b0;
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end
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//-----------------------------------------------------------------
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// Bit half toggle
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i)
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if (rst_i == 1'b1)
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bit_toggle_q <= 1'b0;
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// Time to output a bit?
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else if (bit_out_en_i)
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bit_toggle_q <= ~bit_toggle_q;
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//-----------------------------------------------------------------
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// Output bit (BMC encoded)
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//-----------------------------------------------------------------
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reg bit_r;
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always @ *
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begin
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bit_r = spdif_out_q;
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// Time to output a bit?
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if (bit_out_en_i)
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begin
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// Preamble bits?
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if (bit_count_q < 6'd8)
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begin
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bit_r = preamble_q[bit_count_q[2:0]];
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end
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// Normal timeslots
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else if (bit_count_q < 6'd62)
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begin
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if (subframe_w[bit_count_q / 2] == 1'b0)
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begin
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if (bit_toggle_q == 1'b0)
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bit_r = ~spdif_out_q;
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else
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bit_r = spdif_out_q;
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end
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else
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bit_r = ~spdif_out_q;
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end
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// Parity timeslot
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else
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begin
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// Even number of high bits, make odd
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if (parity_count_q[0] == 1'b0)
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begin
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if (bit_toggle_q == 1'b0)
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bit_r = ~spdif_out_q;
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else
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bit_r = spdif_out_q;
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end
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else
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bit_r = ~spdif_out_q;
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end
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end
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end
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always @ (posedge rst_i or posedge clk_i )
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if (rst_i == 1'b1)
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spdif_out_q <= 1'b0;
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else
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spdif_out_q <= bit_r;
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assign spdif_o = spdif_out_q;
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endmodule
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