54 lines
2.7 KiB
Tcl
54 lines
2.7 KiB
Tcl
# Specify root clocks
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
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create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
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derive_pll_clocks
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# Specify PLL-generated clock(s)
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create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-name SDRAM_CLK [get_ports {SDRAM_CLK}]
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create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
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-name HDMI_CLK [get_ports HDMI_TX_CLK]
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create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
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-name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
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derive_clock_uncertainty
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# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
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set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
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set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
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set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
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-to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-setup 2
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set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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# Decouple different clock groups (to simplify routing)
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set_clock_groups -asynchronous \
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-group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
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-group [get_clocks { *|h2f_user0_clk}] \
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-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
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set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
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set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
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# Put constraints on input ports
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set_false_path -from [get_ports {KEY*}] -to *
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set_false_path -from [get_ports {BTN_*}] -to *
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# Put constraints on output ports
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set_false_path -from * -to [get_ports {LED_*}]
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set_false_path -from * -to [get_ports {VGA_*}]
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set_false_path -from * -to [get_ports {AUDIO_SPDIF}]
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set_false_path -from * -to [get_ports {AUDIO_L}]
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set_false_path -from * -to [get_ports {AUDIO_R}]
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