160 lines
3.5 KiB
Systemverilog
160 lines
3.5 KiB
Systemverilog
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module vip_config
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(
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input clk,
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input reset,
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input [7:0] ARX,
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input [7:0] ARY,
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input CFG_SET,
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input [11:0] WIDTH,
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input [11:0] HFP,
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input [11:0] HBP,
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input [11:0] HS,
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input [11:0] HEIGHT,
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input [11:0] VFP,
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input [11:0] VBP,
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input [11:0] VS,
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input [11:0] VSET,
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output reg [8:0] address,
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output reg write,
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output reg [31:0] writedata,
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input waitrequest
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);
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reg newres = 1;
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wire [21:0] init[23] =
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'{
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//video mode
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{newres, 2'd2, 7'd04, 12'd0 }, //Bank
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{newres, 2'd2, 7'd30, 12'd0 }, //Valid
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{newres, 2'd2, 7'd05, 12'd0 }, //Progressive/Interlaced
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{newres, 2'd2, 7'd06, w }, //Active pixel count
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{newres, 2'd2, 7'd07, h }, //Active line count
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{newres, 2'd2, 7'd09, hfp }, //Horizontal Front Porch
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{newres, 2'd2, 7'd10, hs }, //Horizontal Sync Length
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{newres, 2'd2, 7'd11, hb }, //Horizontal Blanking (HFP+HBP+HSync)
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{newres, 2'd2, 7'd12, vfp }, //Vertical Front Porch
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{newres, 2'd2, 7'd13, vs }, //Vertical Sync Length
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{newres, 2'd2, 7'd14, vb }, //Vertical blanking (VFP+VBP+VSync)
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{newres, 2'd2, 7'd30, 12'd1 }, //Valid
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{newres, 2'd2, 7'd00, 12'd1 }, //Go
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//mixer
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{ 1'd1, 2'd1, 7'd03, w }, //Bkg Width
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{ 1'd1, 2'd1, 7'd04, h }, //Bkg Height
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{ 1'd1, 2'd1, 7'd08, posx }, //Pos X
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{ 1'd1, 2'd1, 7'd09, posy }, //Pos Y
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{ 1'd1, 2'd1, 7'd10, 12'd1 }, //Enable Video 0
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{ 1'd1, 2'd1, 7'd00, 12'd1 }, //Go
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//scaler
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{ 1'd1, 2'd0, 7'd03, videow }, //Output Width
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{ 1'd1, 2'd0, 7'd04, videoh }, //Output Height
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{ 1'd1, 2'd0, 7'd00, 12'd1 }, //Go
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22'h3FFFFF
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};
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reg [11:0] w;
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reg [11:0] hfp;
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reg [11:0] hbp;
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reg [11:0] hs;
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reg [11:0] hb;
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reg [11:0] h;
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reg [11:0] vfp;
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reg [11:0] vbp;
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reg [11:0] vs;
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reg [11:0] vb;
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reg [11:0] videow;
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reg [11:0] videoh;
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reg [11:0] posx;
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reg [11:0] posy;
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always @(posedge clk) begin
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reg [7:0] state = 0;
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reg [7:0] arx, ary;
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reg [7:0] arxd, aryd;
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reg [11:0] vset, vsetd;
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reg cfg, cfgd;
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reg [31:0] wcalc;
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reg [31:0] hcalc;
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reg [12:0] timeout = 0;
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arxd <= ARX;
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aryd <= ARY;
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vsetd <= VSET;
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cfg <= CFG_SET;
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cfgd <= cfg;
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write <= 0;
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if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin
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arx <= arxd;
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ary <= aryd;
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vset <= vsetd;
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timeout <= '1;
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state <= 0;
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if(reset || (~cfgd && cfg)) newres <= 1;
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end
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else
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if(timeout > 0)
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begin
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timeout <= timeout - 1'd1;
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state <= 1;
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if(!(timeout & 'h1f)) case(timeout>>5)
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5: begin
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w <= WIDTH;
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hfp <= HFP;
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hbp <= HBP;
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hs <= HS;
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h <= HEIGHT;
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vfp <= VFP;
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vbp <= VBP;
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vs <= VS;
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end
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4: begin
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hb <= hfp+hbp+hs;
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vb <= vfp+vbp+vs;
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end
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3: begin
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wcalc <= vset ? (vset*arx)/ary : (h*arx)/ary;
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hcalc <= (w*ary)/arx;
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end
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2: begin
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videow <= (!vset && (wcalc > w)) ? w : wcalc[11:0];
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videoh <= vset ? vset : (hcalc > h) ? h : hcalc[11:0];
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end
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1: begin
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posx <= (w - videow)>>1;
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posy <= (h - videoh)>>1;
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end
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endcase
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end
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else
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if(~waitrequest && state)
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begin
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state <= state + 1'd1;
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write <= 0;
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if((state&3)==3) begin
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if(init[state>>2] == 22'h3FFFFF) begin
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state <= 0;
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newres <= 0;
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end
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else begin
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writedata <= 0;
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{write, address, writedata[11:0]} <= init[state>>2];
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end
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end
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end
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end
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endmodule
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