366 lines
11 KiB
Verilog
366 lines
11 KiB
Verilog
/* VIA
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This implementation assumes the I/O data directions and PCR edge triggers used in the Macintosh,
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and ignores most writes to the VIA data direction registers and the PCR.
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The 16 VIA registers are mapped to addresses {8'hEF, 8'b111xxxx1, 8'hFE}:
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0 $0 vBufB register B
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1 $200 ????? register A (controls handshake)
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2 $400 vDirB register B direction register
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3 $600 vDirA register A direction register
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4 $800 vT1C timer 1 counter (low-order byte) - for sound?
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5 $A00 vT1CH timer 1 counter (high-order byte)
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6 $C00 vT1L timer 1 latch (low-order byte)
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7 $E00 vT1LH timer 1 latch (high-order byte)
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8 $1000 vT2C timer 2 counter (low-order byte) - W: writes T2L-L R: read T2C-L and clear interrupt flag
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9 $1200 vT2CH timer 2 counter (high-order byte) - W: write T2C-H, transfer T2L-L to T2C-L, clear interrupt flag R: read T2C-H
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10 $1400 vSR shift register (keyboard)
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11 $1600 vACR auxiliary control register
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12 $1800 vPCR peripheral control register
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13 $1A00 vIFR interrupt flag register
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14 $1C00 vIER interrupt enable register
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15 $1E00 vBufA register A (no handshake)
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Register A:
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Bit(s) Name Dir Description
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7 vSCCWReq in SCC wait/request
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6 vPage2 out Alternate screen buffer (1 = main buffer)
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5 vHeadSel out Disk SEL line
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4 vOverlay out ROM low-memory overlay (1 = overlay on)
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3 vSndPg2 out Alternate sound buffer (1 = main buffer)
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0-2 vSound (mask) out Sound volume
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Register B:
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Bit Name Dir Description
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7 vSndEnb out Sound enable/disable
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6 vH4 in Horizontal blanking
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5 vY2 in Mouse Y2
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4 vX2 in Mouse X2
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3 vSW in Mouse switch
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2 rTCEnb out Real-time clock serial enable (active low I think)
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1 rTCClk out Real-time clock data-clock line
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0 rTCData in/out Real-time clock serial data
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Interrupt flag and enable registers:
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IFR bit 7: remains set (and the IRQ line to the processor is held low) as long as any enabled VIA
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interrupt is occurring.
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IER bit 7: "enable/disable": If bit 7 is a 1, each 1 in bits 0-6 enables the corresponding interrupt;
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if bit 7 is a 0, each 1 in bits 0-6 disables that interrupt. In either case, 0's in bits 0-6 do not
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change the status of those interrupts. Bit 7 is always read as a 1.
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Bit Interrupting device
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7 IRQ (IFR) or enable (IER)
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6 Timer 1 timeout
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5 Timer 2 timeout
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4 Keyboard clock (CB1)
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3 Keyboard data bit (CB2)
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2 Keyboard data ready (completion of 8 shifts) (SR)
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1 Vertical blanking interrupt (CA1)
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0 One-second interrupt (CA2)
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Peripheral control register:
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Bit Description
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5-7 CB2 control (keyboard data bit)
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4 CB1 control (keyboard clock)
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1-3 CA2 control (one-second interrupt)
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0 CA1 control (vertical blanking interrupt)
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1-bit controls: 0 = negative edge trigger (normal Macintosh mode), 1 = positive edge trigger
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3-bit controls:
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000 set IFR on negative edge, clear IFR on read/write from register A/B. Normal Macintosh mode.
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001 set IFR on negative edge
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010 set IFR on positive edge, clear IFR on read/write from register A/B
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011 set IFR on positive edge
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100-111 not used in Macintosh (output mode)
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Auxiliary control register:
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Bit Description
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6-7 T1 control, 00 = one-shot mode, output to PB7 disabled, 11 = free running mode, output to PB7 enabled
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5 T2 control, 0 = interval timer in one-shot mode (Mac mode), 1 = counts a predetermined number of pulses on pin PB6 (not used)
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2-4 shift register control
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1 PB latch enable
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0 PA latch enable
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Timer 2:
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For Macintosh, always operates as a one-shot inerval timer.
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8 $1000 vT2C W: write T2L-L R: read T2C-L and clear interrupt flag
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9 $1200 vT2CH W: write T2C-H, transfer T2L-L to T2C-L, clear interrupt, arms timer flag R: read T2C-H
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*/
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`define INT_ONESEC 0
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`define INT_VBLANK 1
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`define INT_KEYREADY 2
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`define INT_KEYBIT 3
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`define INT_KEYCLK 4
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`define INT_T2 5
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`define INT_T1 6
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module via
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(
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input clk,
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input cep,
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input cen,
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input _reset,
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input selectVIA,
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input _cpuRW,
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input _cpuUDS,
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input [15:0] dataIn,
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input [3:0] cpuAddrRegHi,
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input _hblank,
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input _vblank,
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input mouseY2,
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input mouseX2,
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input mouseButton,
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input rtcData,
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input sccWReq,
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output _irq,
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output [15:0] dataOut,
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output memoryOverlayOn,
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output SEL, // to IWM
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output snd_ena,
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output snd_alt,
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output [2:0] snd_vol,
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input [7:0] kbd_in_data,
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input kbd_in_strobe,
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output [7:0] kbd_out_data,
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output reg kbd_out_strobe
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);
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wire [7:0] dataInHi = dataIn[15:8];
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reg [7:0] dataOutHi;
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assign dataOut = { dataOutHi, 8'hEF };
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reg [7:0] viaADataOut;
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reg [7:0] viaBDataOut;
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reg viaB0DDR;
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reg [6:0] viaIFR;
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reg [6:0] viaIER;
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reg [7:0] viaACR;
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reg [7:0] viaSR;
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reg [15:0] viaTimer1Count;
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reg [15:0] viaTimer1Latch;
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reg [15:0] viaTimer2Count;
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reg [7:0] viaTimer2LatchLow;
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reg viaTimer2Armed;
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// shift register can be written by CPU and by external source
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/* Write to SR (including external input) */
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assign kbd_out_data = viaSR;
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0)
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viaSR <= 8'b0;
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else if(cen) begin
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if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) &&
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(_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA))
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viaSR <= dataInHi;
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if (viaACR[4:2] == 3'b011 && kbd_in_strobe)
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viaSR <= kbd_in_data;
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end
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end
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/* Generate sr_out_strobe */
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0)
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kbd_out_strobe <= 1'b0;
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else if(cen) begin
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if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) &&
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(_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA) &&
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(viaACR[4:2] == 3'b111))
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kbd_out_strobe <= 1;
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else
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kbd_out_strobe <= 0;
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end
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end
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// divide by 10 clock divider for the VIA timers: 0.78336 MHz
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reg [3:0] clkDiv;
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always @(posedge clk) begin
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if(cep) begin
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if (clkDiv == 4'h9)
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clkDiv <= 0;
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else
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clkDiv <= clkDiv + 1'b1;
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end
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end
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wire timerStrobe = (clkDiv == 0);
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// store previous vblank value, for edge detection
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reg _lastVblank;
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always @(posedge clk) if(cen) _lastVblank <= _vblank;
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// count vblanks, and set 1 second interrupt after 60 vblanks
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reg [5:0] vblankCount;
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always @(posedge clk) begin
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if(cen) begin
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if (_vblank == 1'b0 && _lastVblank == 1'b1) begin
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if (vblankCount != 59) begin
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vblankCount <= vblankCount + 1'b1;
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end
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else begin
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vblankCount <= 6'h0;
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end
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end
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end
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end
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assign _irq = (viaIFR & viaIER) == 0 ? 1'b1 : 1'b0;
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// register write
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wire loadT2 = selectVIA == 1'b1 && _cpuUDS == 1'b0 && _cpuRW == 1'b0 && cpuAddrRegHi == 4'h9;
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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viaB0DDR <= 1'b1;
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viaADataOut <= 8'b01111111;
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viaBDataOut <= 8'b11111111;
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viaIFR <= 7'b0000000;
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viaIER <= 7'b0000000;
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viaACR <= 8'b00000000;
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viaTimer1Count <= 16'h0000;
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viaTimer1Latch <= 16'h0000;
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viaTimer2Count <= 16'h0000;
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viaTimer2LatchLow <= 8'h00;
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viaTimer2Armed <= 0;
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end
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else if(cen) begin
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if (selectVIA == 1'b1 && _cpuUDS == 1'b0) begin
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if (_cpuRW == 1'b0) begin
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// normal register writes
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case (cpuAddrRegHi)
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4'h0: // B
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viaBDataOut <= dataInHi;
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4'h2: // B DDR
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viaB0DDR <= dataInHi[0];
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// 4'h3: ignore A DDR
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4'h4: // timer 1 count low
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viaTimer1Count[7:0] <= dataInHi;
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4'h5: // timer 1 count high
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viaTimer1Count[15:8] <= dataInHi;
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4'h6: // timer 1 latch low
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viaTimer1Latch[7:0] <= dataInHi;
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4'h7: // timer 1 latch high
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viaTimer1Latch[15:8] <= dataInHi;
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4'h8: // timer 2 latch low
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viaTimer2LatchLow <= dataInHi;
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4'h9: begin // timer 2 count high
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viaTimer2Count[15:8] <= dataInHi;
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viaTimer2Count[7:0] <= viaTimer2LatchLow;
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viaTimer2Armed = 1'b1;
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viaIFR[`INT_T2] <= 1'b0;
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end
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4'hA: begin // shift register
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if( viaACR[4:2] == 3'b111 )
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viaIFR[`INT_KEYREADY] <= 1'b1;
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end
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4'hB: // Aux control register
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viaACR <= dataInHi;
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// 4'hC: ignore PCR
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4'hD: // IFR
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viaIFR <= viaIFR & ~dataInHi[6:0];
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4'hE: // IER
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if (dataInHi[7])
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viaIER <= viaIER | dataInHi[6:0];
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else
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viaIER <= viaIER & ~dataInHi[6:0];
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4'hF: // A
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viaADataOut <= dataInHi;
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endcase
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end
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else begin
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// interrupt flag modifications due to register reads
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case (cpuAddrRegHi)
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4'h0: begin // reading (and writing?) register B clears KEYCLK and KEYBIT interrupt flags
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viaIFR[`INT_KEYCLK] <= 1'b0;
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viaIFR[`INT_KEYBIT] <= 1'b0;
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end
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4'h8: // reading T2C-L clears the T2 interrupt flag
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viaIFR[`INT_T2] <= 1'b0;
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4'hA: // reading SR clears the SR interrupt flag
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viaIFR[`INT_KEYREADY] <= 1'b0;
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4'hF: begin // reading (and writing?) register A clears VBLANK and ONESEC interrupt flags
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viaIFR[`INT_ONESEC] <= 1'b0;
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viaIFR[`INT_VBLANK] <= 1'b0;
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end
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endcase
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end
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end
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// external interrupts
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if (_vblank == 1'b0 && _lastVblank == 1'b1) begin
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viaIFR[`INT_VBLANK] <= 1'b1; // set vblank interrupt
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if (vblankCount == 59)
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viaIFR[`INT_ONESEC] <= 1'b1; // set one second interrupt after 60 vblanks
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end
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// timer 2
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if (timerStrobe && !loadT2) begin
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if (viaTimer2Armed && viaTimer2Count == 0) begin
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viaIFR[`INT_T2] <= 1'b1;
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viaTimer2Armed <= 0;
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end
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viaTimer2Count <= viaTimer2Count - 1'b1;
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end
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// Shift in under control of external clock
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if (viaACR[4:2] == 3'b011 && kbd_in_strobe)
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viaIFR[`INT_KEYREADY] <= 1;
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end
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end
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// register read
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always @(*) begin
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dataOutHi = 8'hBE;
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case (cpuAddrRegHi)
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4'h0: // B
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// TODO: clear CB1 and CB2 interrupts
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dataOutHi = { viaBDataOut[7], ~_hblank, mouseY2, mouseX2, mouseButton, viaBDataOut[2:1], viaB0DDR == 1'b1 ? viaBDataOut[0] : rtcData };
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4'h2: // B DDR
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dataOutHi = { 7'b1000011, viaB0DDR };
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4'h3: // A DDR
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dataOutHi = 8'b01111111;
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4'h4: // timer 1 count low
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dataOutHi = viaTimer1Count[7:0];
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4'h5: // timer 1 count high
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dataOutHi = viaTimer1Count[15:8];
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4'h6: // timer 1 latch low
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dataOutHi = viaTimer1Latch[7:0];
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4'h7: // timer 1 latch high
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dataOutHi = viaTimer1Latch[15:8];
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4'h8: // timer 2 count low
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dataOutHi = viaTimer2Count[7:0];
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4'h9: // timer 2 count high
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dataOutHi = viaTimer2Count[15:8];
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4'hA: // shift register
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dataOutHi = viaSR;
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4'hB: // Aux control register
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dataOutHi = viaACR;
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4'hC: // PCR
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dataOutHi = 0;
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4'hD: // IFR
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dataOutHi = { viaIFR & viaIER == 0 ? 1'b0 : 1'b1, viaIFR };
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4'hE: // IER
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dataOutHi = { 1'b1, viaIER };
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4'hF: // A
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// TODO: clear CA1 and CA2 interrupts
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dataOutHi = { sccWReq, viaADataOut[6:0] };
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default:
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dataOutHi = 8'hBE;
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endcase
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end
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assign snd_vol = viaADataOut[2:0];
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assign snd_alt = !viaADataOut[3];
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assign snd_ena = viaBDataOut[7];
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assign memoryOverlayOn = viaADataOut[4];
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assign SEL = viaADataOut[5];
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endmodule
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