164 lines
3.8 KiB
Verilog
164 lines
3.8 KiB
Verilog
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module video
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(
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input clk,
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input ce,
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input [14:0] addr,
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input [15:0] dataIn,
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input [1:0] wr,
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output reg hsync,
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output reg vsync,
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output _hblank,
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output _vblank,
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output video_en,
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output pixelOut
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);
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localparam kVisibleWidth = 128,
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kTotalWidth = 176,
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kVisibleHeightStart = 21,
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kVisibleHeightEnd = 362,
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kTotalHeight = 370,
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kHsyncStart = 135,
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kHsyncEnd = 151,
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kVsyncStart = 365,
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kVsyncEnd = 369,
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kPixelLatency = 1; // number of clk8 cycles from xpos==0 to when pixel data actually exits the video shift register
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localparam videoStart = 'hA700 - (kVisibleHeightStart * kVisibleWidth/2);
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reg [7:0] xpos;
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reg [9:0] ypos;
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assign _hblank = ~(xpos >= kVisibleWidth);
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assign _vblank = ~(ypos < kVisibleHeightStart || ypos > kVisibleHeightEnd);
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wire [15:0] scrData;
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vram buff
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(
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.clock(clk),
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.data(dataIn),
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.wraddress(addr[13:0]),
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.byteena_a(wr),
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.wren(ram_wr),
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.rdaddress(videoStart[14:1] + {ypos[8:0], xpos[6:2]}),
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.q(scrData)
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);
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reg ram_wr;
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always @(posedge clk) begin
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reg old_wr;
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old_wr <= |wr;
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ram_wr <= (~old_wr & |wr);
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end
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reg [3:0] cycle;
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always @(posedge clk) if(ce) cycle <= cycle + 1'd1;
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always @(posedge clk) begin
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if(ce && !cycle[1:0]) begin
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if (xpos == kTotalWidth-1) begin
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xpos <= 0;
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if (ypos == kTotalHeight-1) ypos <= 0;
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else ypos <= ypos + 1'b1;
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end else if (!xpos && cycle) begin
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xpos <= 0;
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end else begin
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xpos <= xpos + 1'b1;
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end
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hsync <= (xpos >= kHsyncStart+kPixelLatency && xpos <= kHsyncEnd+kPixelLatency);
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vsync <= (ypos >= kVsyncStart && ypos <= kVsyncEnd);
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end
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end
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// a 0 bit is white, and a 1 bit is black
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// data is shifted out MSB first
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assign pixelOut = ~shiftRegister[15];
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assign video_en = paper[15];
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reg [15:0] shiftRegister;
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reg [15:0] paper;
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always @(posedge clk) begin
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if(ce) begin
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if(_vblank && _hblank && cycle == 2) begin
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shiftRegister <= scrData;
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paper <= 16'hFFFF;
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end
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else begin
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shiftRegister <= { shiftRegister[14:0], 1'b1 };
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paper <= { paper[14:0], 1'b0 };
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end
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end
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end
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endmodule
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module vram
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(
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input clock,
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input [15:0] data,
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input [13:0] wraddress,
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input [1:0] byteena_a,
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input wren,
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input [13:0] rdaddress,
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output [15:0] q
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);
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.address_b (rdaddress),
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.byteena_a (byteena_a),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_b (q),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({16{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.byte_size = 8,
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 16384,
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altsyncram_component.numwords_b = 16384,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.widthad_a = 14,
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altsyncram_component.widthad_b = 14,
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altsyncram_component.width_a = 16,
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altsyncram_component.width_b = 16,
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altsyncram_component.width_byteena_a = 2;
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endmodule
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