mirror of
https://github.com/alxlab-zone66x/Mac_DB15_to_VGA.git
synced 2025-02-05 11:30:48 +00:00
Add Mac DB15 to VGA adapter v1.1 and v1.2
This commit is contained in:
Alexandre Marcoux
parent
79fb15e1b0
commit
e89e5f7cd6
30
README.md
30
README.md
@ -4,12 +4,22 @@
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This is a classic Macintosh DB15 video out to VGA adapter. It's uses the same dip switch settings as the Sony MacView and Unimac 82D.
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[Dip Switch Settings](docs/manuals)
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Dip Switch Settings](docs/manuals)
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The newest versions of the adapter, v1.2, come in 3 flavors now.
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**TH** is all through-hole components like v1.0.
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**MX** has SMD diodes. The rest are through-hole components.
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**SM** has SMD diodes and DIP switches. The rest are through-hole components.
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## Bill of Materials
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### v1.0 TH and v1.2 TH
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| Quantity | Description | Designators | Product Number | Datasheet |
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| :------- | -------------------------- | ---------------------- | ---------------- | ------------------------------------------------------------ |
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| 1 | DB15 | J1 | A-DS 15 A/KG-T4S | [pdf](docs/datasheets/J1_ASS_4888_CO.pdf) |
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@ -17,6 +27,24 @@ This is a classic Macintosh DB15 video out to VGA adapter. It's uses the same di
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| 2 | Dip switch SPST 8 position | SWA1, SWB1 | DS04-254-1L-08BK | [pdf](docs/datasheets/SWA1_SWB1_ds04-254.pdf) |
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| 6 | Diode 1N4148 DO-35 | D1, D2, D3, D4, D5, D6 | 1N4148 | [pdf](docs/datasheets/D1_D2_D3_D4_D5_D6_1N914_D-2309448.pdf) |
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### v1.2 MX
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| Quantity | Description | Designators | Product Number | Datasheet |
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| :------- | -------------------------- | ---------------------- | ---------------- | --------------------------------------------------- |
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| 1 | DB15 | J1 | A-DS 15 A/KG-T4S | [pdf](docs/datasheets/J1_ASS_4888_CO.pdf) |
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| 1 | HD15 | J2 | HD15-SN-25 | [pdf](docs/datasheets/J2_hdxx-sn-25-data-sheet.pdf) |
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| 2 | Dip switch SPST 8 position | SWA1, SWB1 | DS04-254-1L-08BK | [pdf](docs/datasheets/SWA1_SWB1_ds04-254.pdf) |
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| 6 | Diode 1N4148 SOD-123 | D1, D2, D3, D4, D5, D6 | | |
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### v1.2 SM
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| Quantity | Description | Designators | Product Number | Datasheet |
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| :------- | ------------------------------ | ---------------------- | ---------------- | --------------------------------------------------- |
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| 1 | DB15 | J1 | A-DS 15 A/KG-T4S | [pdf](docs/datasheets/J1_ASS_4888_CO.pdf) |
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| 1 | HD15 | J2 | HD15-SN-25 | [pdf](docs/datasheets/J2_hdxx-sn-25-data-sheet.pdf) |
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| 2 | Dip switch SPST 8 position SMD | SWA1, SWB1 | | |
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| 6 | Diode 1N4148 SOD-123 | D1, D2, D3, D4, D5, D6 | | |
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## License
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Binary file not shown.
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Before Width: | Height: | Size: 24 KiB After Width: | Height: | Size: 18 KiB |
BIN
gerbers/Mac DB15 to VGA MX v1.2.zip
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BIN
gerbers/Mac DB15 to VGA MX v1.2.zip
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gerbers/Mac DB15 to VGA SM v1.2.zip
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gerbers/Mac DB15 to VGA SM v1.2.zip
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gerbers/Mac DB15 to VGA TH v1.2.zip
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BIN
gerbers/Mac DB15 to VGA TH v1.2.zip
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kicad/Mac DB15 to VGA MX v1.2-cache.lib
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kicad/Mac DB15 to VGA MX v1.2-cache.lib
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# Diode_1N4148
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#
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DEF Diode_1N4148 D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "Diode_1N4148" 0 -100 50 H V C CNN
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F2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" 0 -175 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS 1N4448 1N4149 1N4151 1N914 BA243 BA244 BA282 BA283 BAV17 BAV18 BAV19 BAV20 BAV21 BAW75 BAW76 BAY93
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$FPLIST
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D*DO?35*
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$ENDFPLIST
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DRAW
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P 2 0 1 10 -50 50 -50 -50 N
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P 2 0 1 0 50 0 -50 0 N
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P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Switch_SW_DIP_x08
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#
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DEF Switch_SW_DIP_x08 SW 0 0 Y N 1 F N
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F0 "SW" 0 550 50 H V C CNN
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F1 "Switch_SW_DIP_x08" 0 -450 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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SW?DIP?x8*
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$ENDFPLIST
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DRAW
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C -80 -300 20 0 0 0 N
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C -80 -200 20 0 0 0 N
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C -80 -100 20 0 0 0 N
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C -80 0 20 0 0 0 N
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C -80 100 20 0 0 0 N
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C -80 200 20 0 0 0 N
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C -80 300 20 0 0 0 N
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C -80 400 20 0 0 0 N
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C 80 -300 20 0 0 0 N
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C 80 -200 20 0 0 0 N
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C 80 -100 20 0 0 0 N
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C 80 0 20 0 0 0 N
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C 80 100 20 0 0 0 N
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C 80 200 20 0 0 0 N
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C 80 300 20 0 0 0 N
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C 80 400 20 0 0 0 N
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S -150 500 150 -400 0 1 10 f
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P 2 0 0 0 -60 -294 93 -253 N
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P 2 0 0 0 -60 -194 93 -153 N
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P 2 0 0 0 -60 -94 93 -53 N
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P 2 0 0 0 -60 5 93 46 N
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P 2 0 0 0 -60 105 93 146 N
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P 2 0 0 0 -60 205 93 246 N
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P 2 0 0 0 -60 305 93 346 N
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P 2 0 0 0 -60 405 93 446 N
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X ~ 1 -300 400 200 R 50 50 1 1 P
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X ~ 10 300 -200 200 L 50 50 1 1 P
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X ~ 11 300 -100 200 L 50 50 1 1 P
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X ~ 12 300 0 200 L 50 50 1 1 P
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X ~ 13 300 100 200 L 50 50 1 1 P
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X ~ 14 300 200 200 L 50 50 1 1 P
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X ~ 15 300 300 200 L 50 50 1 1 P
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X ~ 16 300 400 200 L 50 50 1 1 P
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X ~ 2 -300 300 200 R 50 50 1 1 P
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X ~ 3 -300 200 200 R 50 50 1 1 P
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X ~ 4 -300 100 200 R 50 50 1 1 P
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X ~ 5 -300 0 200 R 50 50 1 1 P
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X ~ 6 -300 -100 200 R 50 50 1 1 P
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X ~ 7 -300 -200 200 R 50 50 1 1 P
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X ~ 8 -300 -300 200 R 50 50 1 1 P
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X ~ 9 300 -300 200 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# project_Mac_DB15_Male_MountingHoles
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#
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DEF project_Mac_DB15_Male_MountingHoles J 0 40 Y N 1 F N
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F0 "J" 100 950 50 H V C CNN
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F1 "project_Mac_DB15_Male_MountingHoles" 100 1025 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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DSUB*Male*
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$ENDFPLIST
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DRAW
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C -50 -600 30 0 1 0 F
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C -50 -400 30 0 1 0 F
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C -50 -200 30 0 1 0 F
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C -50 0 30 0 1 0 F
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C -50 200 30 0 1 0 F
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C -50 400 30 0 1 0 F
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C -50 600 30 0 1 0 F
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C 70 -700 30 0 1 0 F
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C 70 -500 30 0 1 0 F
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C 70 -300 30 0 1 0 F
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C 70 -100 30 0 1 0 F
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C 70 100 30 0 1 0 F
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C 70 300 30 0 1 0 F
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C 70 500 30 0 1 0 F
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C 70 700 30 0 1 0 F
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T 0 -50 660 20 0 0 0 B Normal 0 C T
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T 0 -50 -140 20 0 0 0 B.G Normal 0 C T
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T 0 -50 260 20 0 0 0 C/V.G Normal 0 C T
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T 0 70 360 20 0 0 0 CS Normal 0 C T
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T 0 70 -40 20 0 0 0 G Normal 0 C T
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T 0 70 -240 20 0 0 0 G.G Normal 0 C T
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T 0 -50 -540 20 0 0 0 HS Normal 0 C T
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T 0 -50 -340 20 0 0 0 HS.G Normal 0 C T
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T 0 70 560 20 0 0 0 R Normal 0 C T
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T 0 70 760 20 0 0 0 R.G Normal 0 C T
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T 0 70 160 20 0 0 0 S0 Normal 0 C T
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T 0 65 -440 20 0 0 0 S1 Normal 0 C T
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T 0 -50 460 20 0 0 0 S2 Normal 0 C T
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T 0 -50 60 20 0 0 0 VS Normal 0 C T
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P 2 0 1 0 150 -700 100 -700 N
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P 2 0 1 0 150 -600 -20 -600 N
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P 2 0 1 0 150 -500 100 -500 N
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P 2 0 1 0 150 -400 -20 -400 N
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P 2 0 1 0 150 -300 100 -300 N
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P 2 0 1 0 150 -200 -20 -200 N
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P 2 0 1 0 150 -100 100 -100 N
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P 2 0 1 0 150 0 -20 0 N
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P 2 0 1 0 150 100 100 100 N
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P 2 0 1 0 150 200 -20 200 N
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P 2 0 1 0 150 300 100 300 N
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P 2 0 1 0 150 400 -20 400 N
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P 2 0 1 0 150 500 100 500 N
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P 2 0 1 0 150 600 -20 600 N
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P 2 0 1 0 150 700 100 700 N
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P 5 0 1 10 150 825 -125 675 -125 -675 150 -825 150 825 f
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X SGND 0 0 -900 150 U 50 50 1 1 P
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X RED.GND 1 300 700 150 L 50 50 1 1 P
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X SENSE2 10 300 400 150 L 50 50 1 1 O
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X CSYNC/VSYNC.GND 11 300 200 150 L 50 50 1 1 P
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X /VSYNC 12 300 0 150 L 50 50 1 1 I
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X BLU.GND 13 300 -200 150 L 50 50 1 1 P
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X HSYNC.GND 14 300 -400 150 L 50 50 1 1 P
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X /HSYNC 15 300 -600 150 L 50 50 1 1 I
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X RED.VID 2 300 500 150 L 50 50 1 1 I
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X /CSYNC 3 300 300 150 L 50 50 1 1 I
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X SENSE0 4 300 100 150 L 50 50 1 1 O
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X GRN.VID 5 300 -100 150 L 50 50 1 1 I
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X GRN.GND 6 300 -300 150 L 50 50 1 1 P
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X SENSE1 7 300 -500 150 L 50 50 1 1 O
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X 8 8 300 -700 150 L 50 50 1 1 N N
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X BLU.VID 9 300 600 150 L 50 50 1 1 O
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ENDDRAW
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ENDDEF
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#
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# project_VGA_DB15_Female_HighDensity_MountingHoles
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#
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DEF project_VGA_DB15_Female_HighDensity_MountingHoles J 0 40 Y N 1 F N
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F0 "J" 0 850 50 H V C CNN
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F1 "project_VGA_DB15_Female_HighDensity_MountingHoles" 0 750 50 H V C CNN
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F2 "" -950 400 50 H I C CNN
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F3 "" -950 400 50 H I C CNN
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$FPLIST
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DSUB*Female*
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$ENDFPLIST
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DRAW
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C -75 -400 25 0 1 0 N
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C -75 -200 25 0 1 0 N
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C -75 0 25 0 1 0 N
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C -75 200 25 0 1 0 N
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C -75 400 25 0 1 0 N
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C 0 -300 25 0 1 0 N
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C 0 -100 25 0 1 0 N
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C 0 100 25 0 1 0 N
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C 0 300 25 0 1 0 N
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C 0 500 25 0 1 0 N
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C 75 -400 25 0 1 0 N
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C 75 -200 25 0 1 0 N
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C 75 0 25 0 1 0 N
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C 75 200 25 0 1 0 N
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C 75 400 25 0 1 0 N
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T 0 -75 -50 20 0 0 0 B Normal 0 C B
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T 0 0 50 20 0 0 0 B.G Normal 0 C B
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T 0 -75 150 20 0 0 0 G Normal 0 C B
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T 0 0 250 20 0 0 0 G.G Normal 0 C B
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T 0 -75 -450 20 0 0 0 GND Normal 0 C C
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T 0 75 -50 20 0 0 0 HS Normal 0 C B
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T 0 75 350 20 0 0 0 ID0 Normal 0 C B
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T 0 75 150 20 0 0 0 ID1 Normal 0 C B
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T 0 -75 -250 20 0 0 0 ID2 Normal 0 C B
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T 0 75 -450 20 0 0 0 ID3 Normal 0 C C
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T 0 0 -150 20 0 0 0 KEY Normal 0 C B
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T 0 -75 350 20 0 0 0 R Normal 0 C B
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T 0 0 450 20 0 0 0 R.G Normal 0 C B
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T 0 0 -350 20 0 0 0 S.G Normal 0 C B
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T 0 75 -250 20 0 0 0 VS Normal 0 C B
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P 2 0 1 0 -125 300 -25 300 N
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P 2 0 1 0 -25 -300 -125 -300 N
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P 2 0 1 0 -25 -100 -125 -100 N
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P 2 0 1 0 -25 100 -125 100 N
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P 2 0 1 0 -25 500 -125 500 N
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P 5 0 1 10 -150 700 -150 -600 150 -500 150 600 -150 700 f
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X SGND 0 0 -700 150 U 50 50 1 1 P
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X RED.VID 1 -300 400 200 R 50 50 1 1 O
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X SYNC.GND 10 -300 -300 200 R 50 50 1 1 P
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X ID0 11 300 400 200 L 50 50 1 1 I
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X ID1 12 300 200 200 L 50 50 1 1 I
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X /HSYNC 13 300 0 200 L 50 50 1 1 O
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X /VSYNC 14 300 -200 200 L 50 50 1 1 O
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X ID3 15 300 -400 200 L 50 50 1 1 I
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X GRN.VID 2 -300 200 200 R 50 50 1 1 O
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X BLU.VID 3 -300 0 200 R 50 50 1 1 O
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X ID2/RES 4 -300 -200 200 R 50 50 1 1 I
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X GND 5 -300 -400 200 R 50 50 1 1 P
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X RED.GND 6 -300 500 200 R 50 50 1 1 P
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X GRN.GND 7 -300 300 200 R 50 50 1 1 P
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X BLU.GND 8 -300 100 200 R 50 50 1 1 P
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X KEY 9 -300 -100 200 R 50 50 1 1 w
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ENDDRAW
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ENDDEF
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#
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#End Library
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3360
kicad/Mac DB15 to VGA MX v1.2.kicad_pcb
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3360
kicad/Mac DB15 to VGA MX v1.2.kicad_pcb
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File diff suppressed because it is too large
Load Diff
77
kicad/Mac DB15 to VGA MX v1.2.kicad_prl
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77
kicad/Mac DB15 to VGA MX v1.2.kicad_prl
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{
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"board": {
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"active_layer": 0,
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"active_layer_preset": "",
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"auto_track_width": true,
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"hidden_nets": [],
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"high_contrast_mode": 0,
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"net_color_mode": 1,
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"opacity": {
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"pads": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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},
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"ratsnest_display_mode": 0,
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"selection_filter": {
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"dimensions": true,
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"footprints": true,
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"graphics": true,
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"keepouts": true,
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"lockedItems": true,
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"otherItems": true,
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"pads": true,
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"text": true,
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"tracks": true,
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"vias": true,
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"zones": true
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},
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"visible_items": [
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0,
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1,
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2,
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3,
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4,
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],
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"visible_layers": "fffffff_ffffffff",
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"zone_display_mode": 0
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},
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"meta": {
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"filename": "Mac DB15 to VGA MX v1.2.kicad_prl",
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"version": 3
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},
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"project": {
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"files": []
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}
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}
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201
kicad/Mac DB15 to VGA MX v1.2.kicad_pro
Normal file
201
kicad/Mac DB15 to VGA MX v1.2.kicad_pro
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.762,
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"height": 1.524,
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"width": 1.524
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},
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"silk_line_width": 0.12,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15,
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||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.127
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rule_severitieslegacy_courtyards_overlap": false,
|
||||
"rule_severitieslegacy_no_courtyard_defined": false,
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.024999999999999998,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.127,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.6,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.5
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA MX v1.2.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.127,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.127,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "Mac DB-15 to VGA TH v1.0.net",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"drawing": {
|
||||
"default_text_size": 50,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"net_format_name": "Pcbnew",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
||||
251
kicad/Mac DB15 to VGA MX v1.2.pro
Normal file
251
kicad/Mac DB15 to VGA MX v1.2.pro
Normal file
@ -0,0 +1,251 @@
|
||||
update=1/26/2022 3:39:52 PM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=Mac DB-15 to VGA TH v1.0.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=0
|
||||
MinTrackWidth=0.127
|
||||
MinViaDiameter=0.6
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.127
|
||||
TrackWidth2=0.5
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.05
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.127
|
||||
TrackWidth=0.127
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
427
kicad/Mac DB15 to VGA MX v1.2.sch
Normal file
427
kicad/Mac DB15 to VGA MX v1.2.sch
Normal file
@ -0,0 +1,427 @@
|
||||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Diode:1N4148 D2
|
||||
U 1 1 61588880
|
||||
P 4750 4800
|
||||
F 0 "D2" H 4750 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4926 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 4750 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4800 50 0001 C CNN
|
||||
1 4750 4800
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3750 4350 4050 4350
|
||||
Wire Wire Line
|
||||
4900 4450 5200 4450
|
||||
Wire Wire Line
|
||||
4900 4800 5200 4800
|
||||
Text Label 4950 4450 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 4950 4800 0 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
4600 4800 4300 4800
|
||||
Wire Wire Line
|
||||
4600 4450 4300 4450
|
||||
Text Label 5650 4050 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
5550 4250 5550 4150
|
||||
Text Label 5650 4250 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 9100 5050 0 50 ~ 0
|
||||
GND.S
|
||||
Wire Wire Line
|
||||
9350 4400 9050 4400
|
||||
Wire Wire Line
|
||||
8900 3400 8900 3600
|
||||
Wire Wire Line
|
||||
9950 3700 10250 3700
|
||||
Wire Wire Line
|
||||
8900 4500 8900 4300
|
||||
Wire Wire Line
|
||||
9350 4500 8900 4500
|
||||
Connection ~ 8900 4300
|
||||
Connection ~ 8900 3600
|
||||
Connection ~ 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 9350 4300
|
||||
Wire Wire Line
|
||||
9650 4800 9650 5050
|
||||
Wire Wire Line
|
||||
9350 3600 8900 3600
|
||||
Wire Wire Line
|
||||
9050 3700 9350 3700
|
||||
Wire Wire Line
|
||||
8900 3800 9350 3800
|
||||
Wire Wire Line
|
||||
8900 4000 9350 4000
|
||||
Wire Wire Line
|
||||
8900 3800 8900 4000
|
||||
Connection ~ 8900 3800
|
||||
Wire Wire Line
|
||||
8900 3600 8900 3800
|
||||
NoConn ~ 9350 4200
|
||||
NoConn ~ 9950 4500
|
||||
NoConn ~ 9950 3900
|
||||
Text Label 2150 3700 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 2150 4600 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 2150 4000 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 2150 3800 0 50 ~ 0
|
||||
CS
|
||||
Text Label 2150 3600 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
7550 4450 7200 4450
|
||||
Wire Wire Line
|
||||
7550 4800 7200 4800
|
||||
Text Label 7950 4800 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 7950 4450 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
7850 4800 8200 4800
|
||||
Wire Wire Line
|
||||
7850 4450 8200 4450
|
||||
$Comp
|
||||
L Diode:1N4148 D3
|
||||
U 1 1 615851AF
|
||||
P 7700 4450
|
||||
F 0 "D3" H 7700 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4576 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 7700 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4450 50 0001 C CNN
|
||||
1 7700 4450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2100 4600 2400 4600
|
||||
Wire Wire Line
|
||||
2100 4000 2400 4000
|
||||
Wire Wire Line
|
||||
2100 3800 2400 3800
|
||||
Wire Wire Line
|
||||
2100 3600 2400 3600
|
||||
Wire Wire Line
|
||||
2100 4700 2400 4700
|
||||
Wire Wire Line
|
||||
2100 4500 2400 4500
|
||||
Wire Wire Line
|
||||
2100 3900 2400 3900
|
||||
Wire Wire Line
|
||||
2100 3700 2400 3700
|
||||
Wire Wire Line
|
||||
1800 5050 1800 5000
|
||||
Text Label 7950 4050 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 7950 3700 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
7850 4050 8200 4050
|
||||
Wire Wire Line
|
||||
7850 3700 8200 3700
|
||||
$Comp
|
||||
L Diode:1N4148 D5
|
||||
U 1 1 61587AEA
|
||||
P 7700 3700
|
||||
F 0 "D5" H 7700 3917 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 3826 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 7700 3525 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 3700 50 0001 C CNN
|
||||
1 7700 3700
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D6
|
||||
U 1 1 615862A9
|
||||
P 7700 4050
|
||||
F 0 "D6" H 7700 4267 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4176 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 7700 3875 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4050 50 0001 C CNN
|
||||
1 7700 4050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D4
|
||||
U 1 1 6158496F
|
||||
P 7700 4800
|
||||
F 0 "D4" H 7700 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4926 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 7700 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4800 50 0001 C CNN
|
||||
1 7700 4800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2800 4350 3150 4350
|
||||
Text Label 3100 4350 2 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
2800 4450 3150 4450
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4450
|
||||
Wire Wire Line
|
||||
4050 4450 3750 4450
|
||||
Connection ~ 4050 4350
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4250
|
||||
Connection ~ 4050 4250
|
||||
Wire Wire Line
|
||||
4050 4250 3750 4250
|
||||
Wire Wire Line
|
||||
4050 4250 4050 4150
|
||||
Wire Wire Line
|
||||
4050 4150 3750 4150
|
||||
Text Label 9100 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4300 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3600 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3800 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4000 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 4300 2400 4300
|
||||
Text Label 2150 3400 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:Mac_DB15_Male_MountingHoles J1
|
||||
U 1 1 6154A803
|
||||
P 1800 4100
|
||||
F 0 "J1" H 1894 5092 50 0000 C CNN
|
||||
F 1 "Mac_DB15_Male_MountingHoles" H 1894 5001 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm" H 1800 4100 50 0001 C CNN
|
||||
F 3 " ~" H 1800 4100 50 0001 C CNN
|
||||
1 1800 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 2150 4300 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:VGA_DB15_Female_HighDensity_MountingHoles J2
|
||||
U 1 1 6151FC86
|
||||
P 9650 4100
|
||||
F 0 "J2" H 9650 4967 50 0000 C CNN
|
||||
F 1 "VGA_DB15_Female_HighDensity_MountingHoles" H 9650 4876 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm" H 8700 4500 50 0001 C CNN
|
||||
F 3 " ~" H 8700 4500 50 0001 C CNN
|
||||
1 9650 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 9100 3700 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
5900 4050 5550 4050
|
||||
Text Label 10000 3700 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 3900 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4400 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4200 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
9350 3900 9050 3900
|
||||
Text Label 9100 3900 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
2100 4400 2400 4400
|
||||
Text Label 2150 4400 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3500 2400 3500
|
||||
Text Label 2150 3500 0 50 ~ 0
|
||||
B
|
||||
Wire Wire Line
|
||||
9350 4100 9050 4100
|
||||
Text Label 9100 4100 0 50 ~ 0
|
||||
B
|
||||
$Comp
|
||||
L Diode:1N4148 D1
|
||||
U 1 1 61582C6F
|
||||
P 4750 4450
|
||||
F 0 "D1" H 4750 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4576 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 4750 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4450 50 0001 C CNN
|
||||
1 4750 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 3100 4150 2 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
2800 4150 3150 4150
|
||||
Text Label 3100 4250 2 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
2800 4250 3150 4250
|
||||
Wire Wire Line
|
||||
2800 4050 3150 4050
|
||||
Wire Wire Line
|
||||
5900 3950 5550 3950
|
||||
Wire Wire Line
|
||||
5550 3950 5550 4050
|
||||
Wire Wire Line
|
||||
2100 4100 2400 4100
|
||||
Text Label 2150 4100 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4050 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4450 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3400 8900 3400
|
||||
Wire Wire Line
|
||||
5550 3850 5900 3850
|
||||
Text Label 5650 3850 0 50 ~ 0
|
||||
CS
|
||||
Text Label 5650 4450 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
5550 4450 5900 4450
|
||||
Wire Wire Line
|
||||
5550 4350 5900 4350
|
||||
Wire Wire Line
|
||||
5550 4350 5550 4450
|
||||
Wire Wire Line
|
||||
8200 3700 8200 4050
|
||||
Wire Wire Line
|
||||
8200 4450 8200 4800
|
||||
Wire Wire Line
|
||||
2100 4200 2400 4200
|
||||
Wire Wire Line
|
||||
5200 4450 5200 4800
|
||||
Wire Wire Line
|
||||
5900 4250 5550 4250
|
||||
Wire Wire Line
|
||||
5550 4150 5900 4150
|
||||
Text Label 2150 4700 0 50 ~ 0
|
||||
HS
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWB1
|
||||
U 1 1 6152990A
|
||||
P 6200 4050
|
||||
F 0 "SWB1" H 6200 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 6200 4626 50 0000 C CNN
|
||||
F 2 "project:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" H 6200 4050 50 0001 C CNN
|
||||
F 3 "~" H 6200 4050 50 0001 C CNN
|
||||
1 6200 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5900 3750 5550 3750
|
||||
Text Label 5650 3750 0 50 ~ 0
|
||||
HS
|
||||
Wire Wire Line
|
||||
6500 3750 6900 3750
|
||||
Wire Wire Line
|
||||
9950 4100 10250 4100
|
||||
Text Label 10000 4100 0 50 ~ 0
|
||||
HS-CS
|
||||
Wire Wire Line
|
||||
3750 4050 4050 4050
|
||||
Text Label 3800 4050 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
9950 4300 10250 4300
|
||||
Text Label 10000 4300 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
6500 4450 6900 4450
|
||||
Wire Wire Line
|
||||
6500 4350 6900 4350
|
||||
Text Label 4450 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 4450 4800 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4350 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 7350 4800 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
6500 4250 6900 4250
|
||||
Text Label 6600 4250 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
7550 3700 7200 3700
|
||||
Wire Wire Line
|
||||
7550 4050 7200 4050
|
||||
Wire Wire Line
|
||||
6500 4150 6900 4150
|
||||
Text Label 6600 4150 0 50 ~ 0
|
||||
D3
|
||||
Text Label 7350 4450 0 50 ~ 0
|
||||
D3
|
||||
Wire Wire Line
|
||||
6500 4050 6900 4050
|
||||
Wire Wire Line
|
||||
6500 3950 6900 3950
|
||||
Text Label 6600 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 3700 0 50 ~ 0
|
||||
D5
|
||||
Wire Wire Line
|
||||
6500 3850 6900 3850
|
||||
Wire Wire Line
|
||||
6900 3850 6900 3750
|
||||
Text Label 6600 3950 0 50 ~ 0
|
||||
D5
|
||||
Text Label 6600 3850 0 50 ~ 0
|
||||
HS-CS
|
||||
Text Notes 7050 6700 0 50 ~ 0
|
||||
Sony MacView / Unimac 82D Schematics
|
||||
Text Notes 7050 6800 0 50 ~ 0
|
||||
CC BY-NC-SA 4.0
|
||||
Text Notes 7400 7500 0 50 ~ 0
|
||||
DB-15 to VGA TH v1.0
|
||||
Text Notes 8150 7650 0 50 ~ 0
|
||||
November 18, 2021
|
||||
Wire Wire Line
|
||||
1800 5050 9650 5050
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWA1
|
||||
U 1 1 61528095
|
||||
P 3450 4050
|
||||
F 0 "SWA1" H 3450 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 3450 4626 50 0000 C CNN
|
||||
F 2 "project:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" H 3450 4050 50 0001 C CNN
|
||||
F 3 "~" H 3450 4050 50 0001 C CNN
|
||||
1 3450 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
NoConn ~ 3750 3750
|
||||
NoConn ~ 3750 3850
|
||||
NoConn ~ 3750 3950
|
||||
NoConn ~ 3150 3950
|
||||
NoConn ~ 3150 3850
|
||||
NoConn ~ 3150 3750
|
||||
$EndSCHEMATC
|
||||
3864
kicad/Mac DB15 to VGA SM v1.2.kicad_pcb
Normal file
3864
kicad/Mac DB15 to VGA SM v1.2.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
251
kicad/Mac DB15 to VGA SM v1.2.pro
Normal file
251
kicad/Mac DB15 to VGA SM v1.2.pro
Normal file
@ -0,0 +1,251 @@
|
||||
update=1/26/2022 3:39:52 PM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=Mac DB-15 to VGA TH v1.0.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=0
|
||||
MinTrackWidth=0.127
|
||||
MinViaDiameter=0.6
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.127
|
||||
TrackWidth2=0.5
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.05
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.127
|
||||
TrackWidth=0.127
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
427
kicad/Mac DB15 to VGA SM v1.2.sch
Normal file
427
kicad/Mac DB15 to VGA SM v1.2.sch
Normal file
@ -0,0 +1,427 @@
|
||||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Diode:1N4148 D2
|
||||
U 1 1 61588880
|
||||
P 4750 4800
|
||||
F 0 "D2" H 4750 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4926 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 4750 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4800 50 0001 C CNN
|
||||
1 4750 4800
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3750 4350 4050 4350
|
||||
Wire Wire Line
|
||||
4900 4450 5200 4450
|
||||
Wire Wire Line
|
||||
4900 4800 5200 4800
|
||||
Text Label 4950 4450 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 4950 4800 0 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
4600 4800 4300 4800
|
||||
Wire Wire Line
|
||||
4600 4450 4300 4450
|
||||
Text Label 5650 4050 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
5550 4250 5550 4150
|
||||
Text Label 5650 4250 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 9100 5050 0 50 ~ 0
|
||||
GND.S
|
||||
Wire Wire Line
|
||||
9350 4400 9050 4400
|
||||
Wire Wire Line
|
||||
8900 3400 8900 3600
|
||||
Wire Wire Line
|
||||
9950 3700 10250 3700
|
||||
Wire Wire Line
|
||||
8900 4500 8900 4300
|
||||
Wire Wire Line
|
||||
9350 4500 8900 4500
|
||||
Connection ~ 8900 4300
|
||||
Connection ~ 8900 3600
|
||||
Connection ~ 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 9350 4300
|
||||
Wire Wire Line
|
||||
9650 4800 9650 5050
|
||||
Wire Wire Line
|
||||
9350 3600 8900 3600
|
||||
Wire Wire Line
|
||||
9050 3700 9350 3700
|
||||
Wire Wire Line
|
||||
8900 3800 9350 3800
|
||||
Wire Wire Line
|
||||
8900 4000 9350 4000
|
||||
Wire Wire Line
|
||||
8900 3800 8900 4000
|
||||
Connection ~ 8900 3800
|
||||
Wire Wire Line
|
||||
8900 3600 8900 3800
|
||||
NoConn ~ 9350 4200
|
||||
NoConn ~ 9950 4500
|
||||
NoConn ~ 9950 3900
|
||||
Text Label 2150 3700 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 2150 4600 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 2150 4000 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 2150 3800 0 50 ~ 0
|
||||
CS
|
||||
Text Label 2150 3600 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
7550 4450 7200 4450
|
||||
Wire Wire Line
|
||||
7550 4800 7200 4800
|
||||
Text Label 7950 4800 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 7950 4450 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
7850 4800 8200 4800
|
||||
Wire Wire Line
|
||||
7850 4450 8200 4450
|
||||
$Comp
|
||||
L Diode:1N4148 D3
|
||||
U 1 1 615851AF
|
||||
P 7700 4450
|
||||
F 0 "D3" H 7700 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4576 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 7700 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4450 50 0001 C CNN
|
||||
1 7700 4450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2100 4600 2400 4600
|
||||
Wire Wire Line
|
||||
2100 4000 2400 4000
|
||||
Wire Wire Line
|
||||
2100 3800 2400 3800
|
||||
Wire Wire Line
|
||||
2100 3600 2400 3600
|
||||
Wire Wire Line
|
||||
2100 4700 2400 4700
|
||||
Wire Wire Line
|
||||
2100 4500 2400 4500
|
||||
Wire Wire Line
|
||||
2100 3900 2400 3900
|
||||
Wire Wire Line
|
||||
2100 3700 2400 3700
|
||||
Wire Wire Line
|
||||
1800 5050 1800 5000
|
||||
Text Label 7950 4050 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 7950 3700 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
7850 4050 8200 4050
|
||||
Wire Wire Line
|
||||
7850 3700 8200 3700
|
||||
$Comp
|
||||
L Diode:1N4148 D5
|
||||
U 1 1 61587AEA
|
||||
P 7700 3700
|
||||
F 0 "D5" H 7700 3917 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 3826 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 7700 3525 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 3700 50 0001 C CNN
|
||||
1 7700 3700
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D6
|
||||
U 1 1 615862A9
|
||||
P 7700 4050
|
||||
F 0 "D6" H 7700 4267 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4176 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 7700 3875 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4050 50 0001 C CNN
|
||||
1 7700 4050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D4
|
||||
U 1 1 6158496F
|
||||
P 7700 4800
|
||||
F 0 "D4" H 7700 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4926 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 7700 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4800 50 0001 C CNN
|
||||
1 7700 4800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2800 4350 3150 4350
|
||||
Text Label 3100 4350 2 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
2800 4450 3150 4450
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4450
|
||||
Wire Wire Line
|
||||
4050 4450 3750 4450
|
||||
Connection ~ 4050 4350
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4250
|
||||
Connection ~ 4050 4250
|
||||
Wire Wire Line
|
||||
4050 4250 3750 4250
|
||||
Wire Wire Line
|
||||
4050 4250 4050 4150
|
||||
Wire Wire Line
|
||||
4050 4150 3750 4150
|
||||
Text Label 9100 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4300 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3600 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3800 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4000 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 4300 2400 4300
|
||||
Text Label 2150 3400 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:Mac_DB15_Male_MountingHoles J1
|
||||
U 1 1 6154A803
|
||||
P 1800 4100
|
||||
F 0 "J1" H 1894 5092 50 0000 C CNN
|
||||
F 1 "Mac_DB15_Male_MountingHoles" H 1894 5001 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm" H 1800 4100 50 0001 C CNN
|
||||
F 3 " ~" H 1800 4100 50 0001 C CNN
|
||||
1 1800 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 2150 4300 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:VGA_DB15_Female_HighDensity_MountingHoles J2
|
||||
U 1 1 6151FC86
|
||||
P 9650 4100
|
||||
F 0 "J2" H 9650 4967 50 0000 C CNN
|
||||
F 1 "VGA_DB15_Female_HighDensity_MountingHoles" H 9650 4876 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm" H 8700 4500 50 0001 C CNN
|
||||
F 3 " ~" H 8700 4500 50 0001 C CNN
|
||||
1 9650 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 9100 3700 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
5900 4050 5550 4050
|
||||
Text Label 10000 3700 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 3900 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4400 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4200 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
9350 3900 9050 3900
|
||||
Text Label 9100 3900 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
2100 4400 2400 4400
|
||||
Text Label 2150 4400 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3500 2400 3500
|
||||
Text Label 2150 3500 0 50 ~ 0
|
||||
B
|
||||
Wire Wire Line
|
||||
9350 4100 9050 4100
|
||||
Text Label 9100 4100 0 50 ~ 0
|
||||
B
|
||||
$Comp
|
||||
L Diode:1N4148 D1
|
||||
U 1 1 61582C6F
|
||||
P 4750 4450
|
||||
F 0 "D1" H 4750 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4576 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SOD-123" H 4750 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4450 50 0001 C CNN
|
||||
1 4750 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 3100 4150 2 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
2800 4150 3150 4150
|
||||
Text Label 3100 4250 2 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
2800 4250 3150 4250
|
||||
Wire Wire Line
|
||||
2800 4050 3150 4050
|
||||
Wire Wire Line
|
||||
5900 3950 5550 3950
|
||||
Wire Wire Line
|
||||
5550 3950 5550 4050
|
||||
Wire Wire Line
|
||||
2100 4100 2400 4100
|
||||
Text Label 2150 4100 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4050 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4450 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3400 8900 3400
|
||||
Wire Wire Line
|
||||
5550 3850 5900 3850
|
||||
Text Label 5650 3850 0 50 ~ 0
|
||||
CS
|
||||
Text Label 5650 4450 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
5550 4450 5900 4450
|
||||
Wire Wire Line
|
||||
5550 4350 5900 4350
|
||||
Wire Wire Line
|
||||
5550 4350 5550 4450
|
||||
Wire Wire Line
|
||||
8200 3700 8200 4050
|
||||
Wire Wire Line
|
||||
8200 4450 8200 4800
|
||||
Wire Wire Line
|
||||
2100 4200 2400 4200
|
||||
Wire Wire Line
|
||||
5200 4450 5200 4800
|
||||
Wire Wire Line
|
||||
5900 4250 5550 4250
|
||||
Wire Wire Line
|
||||
5550 4150 5900 4150
|
||||
Text Label 2150 4700 0 50 ~ 0
|
||||
HS
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWB1
|
||||
U 1 1 6152990A
|
||||
P 6200 4050
|
||||
F 0 "SWB1" H 6200 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 6200 4626 50 0000 C CNN
|
||||
F 2 "Button_Switch_SMD:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W8.61mm_P2.54mm" H 6200 4050 50 0001 C CNN
|
||||
F 3 "~" H 6200 4050 50 0001 C CNN
|
||||
1 6200 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5900 3750 5550 3750
|
||||
Text Label 5650 3750 0 50 ~ 0
|
||||
HS
|
||||
Wire Wire Line
|
||||
6500 3750 6900 3750
|
||||
Wire Wire Line
|
||||
9950 4100 10250 4100
|
||||
Text Label 10000 4100 0 50 ~ 0
|
||||
HS-CS
|
||||
Wire Wire Line
|
||||
3750 4050 4050 4050
|
||||
Text Label 3800 4050 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
9950 4300 10250 4300
|
||||
Text Label 10000 4300 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
6500 4450 6900 4450
|
||||
Wire Wire Line
|
||||
6500 4350 6900 4350
|
||||
Text Label 4450 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 4450 4800 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4350 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 7350 4800 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
6500 4250 6900 4250
|
||||
Text Label 6600 4250 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
7550 3700 7200 3700
|
||||
Wire Wire Line
|
||||
7550 4050 7200 4050
|
||||
Wire Wire Line
|
||||
6500 4150 6900 4150
|
||||
Text Label 6600 4150 0 50 ~ 0
|
||||
D3
|
||||
Text Label 7350 4450 0 50 ~ 0
|
||||
D3
|
||||
Wire Wire Line
|
||||
6500 4050 6900 4050
|
||||
Wire Wire Line
|
||||
6500 3950 6900 3950
|
||||
Text Label 6600 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 3700 0 50 ~ 0
|
||||
D5
|
||||
Wire Wire Line
|
||||
6500 3850 6900 3850
|
||||
Wire Wire Line
|
||||
6900 3850 6900 3750
|
||||
Text Label 6600 3950 0 50 ~ 0
|
||||
D5
|
||||
Text Label 6600 3850 0 50 ~ 0
|
||||
HS-CS
|
||||
Text Notes 7050 6700 0 50 ~ 0
|
||||
Sony MacView / Unimac 82D Schematics
|
||||
Text Notes 7050 6800 0 50 ~ 0
|
||||
CC BY-NC-SA 4.0
|
||||
Text Notes 7400 7500 0 50 ~ 0
|
||||
DB-15 to VGA TH v1.0
|
||||
Text Notes 8150 7650 0 50 ~ 0
|
||||
November 18, 2021
|
||||
Wire Wire Line
|
||||
1800 5050 9650 5050
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWA1
|
||||
U 1 1 61528095
|
||||
P 3450 4050
|
||||
F 0 "SWA1" H 3450 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 3450 4626 50 0000 C CNN
|
||||
F 2 "Button_Switch_SMD:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W8.61mm_P2.54mm" H 3450 4050 50 0001 C CNN
|
||||
F 3 "~" H 3450 4050 50 0001 C CNN
|
||||
1 3450 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
NoConn ~ 3750 3750
|
||||
NoConn ~ 3750 3850
|
||||
NoConn ~ 3750 3950
|
||||
NoConn ~ 3150 3950
|
||||
NoConn ~ 3150 3850
|
||||
NoConn ~ 3150 3750
|
||||
$EndSCHEMATC
|
||||
3170
kicad/Mac DB15 to VGA TH v1.1.kicad_pcb
Normal file
3170
kicad/Mac DB15 to VGA TH v1.1.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
77
kicad/Mac DB15 to VGA TH v1.1.kicad_prl
Normal file
77
kicad/Mac DB15 to VGA TH v1.1.kicad_prl
Normal file
@ -0,0 +1,77 @@
|
||||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"ratsnest_display_mode": 0,
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
32,
|
||||
33,
|
||||
34,
|
||||
35,
|
||||
36
|
||||
],
|
||||
"visible_layers": "fffffff_ffffffff",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA TH v1.1.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
||||
201
kicad/Mac DB15 to VGA TH v1.1.kicad_pro
Normal file
201
kicad/Mac DB15 to VGA TH v1.1.kicad_pro
Normal file
@ -0,0 +1,201 @@
|
||||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.127
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rule_severitieslegacy_courtyards_overlap": false,
|
||||
"rule_severitieslegacy_no_courtyard_defined": false,
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.024999999999999998,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.127,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.6,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.5
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA TH v1.1.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.127,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.127,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "Mac DB-15 to VGA TH v1.0.net",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"drawing": {
|
||||
"default_text_size": 50,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"net_format_name": "Pcbnew",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
||||
251
kicad/Mac DB15 to VGA TH v1.1.pro
Normal file
251
kicad/Mac DB15 to VGA TH v1.1.pro
Normal file
@ -0,0 +1,251 @@
|
||||
update=1/26/2022 3:39:52 PM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=Mac DB-15 to VGA TH v1.0.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=0
|
||||
MinTrackWidth=0.127
|
||||
MinViaDiameter=0.6
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.127
|
||||
TrackWidth2=0.5
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.05
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.127
|
||||
TrackWidth=0.127
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
427
kicad/Mac DB15 to VGA TH v1.1.sch
Normal file
427
kicad/Mac DB15 to VGA TH v1.1.sch
Normal file
@ -0,0 +1,427 @@
|
||||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Diode:1N4148 D2
|
||||
U 1 1 61588880
|
||||
P 4750 4800
|
||||
F 0 "D2" H 4750 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4926 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 4750 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4800 50 0001 C CNN
|
||||
1 4750 4800
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3750 4350 4050 4350
|
||||
Wire Wire Line
|
||||
4900 4450 5200 4450
|
||||
Wire Wire Line
|
||||
4900 4800 5200 4800
|
||||
Text Label 4950 4450 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 4950 4800 0 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
4600 4800 4300 4800
|
||||
Wire Wire Line
|
||||
4600 4450 4300 4450
|
||||
Text Label 5650 4050 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
5550 4250 5550 4150
|
||||
Text Label 5650 4250 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 9100 5050 0 50 ~ 0
|
||||
GND.S
|
||||
Wire Wire Line
|
||||
9350 4400 9050 4400
|
||||
Wire Wire Line
|
||||
8900 3400 8900 3600
|
||||
Wire Wire Line
|
||||
9950 3700 10250 3700
|
||||
Wire Wire Line
|
||||
8900 4500 8900 4300
|
||||
Wire Wire Line
|
||||
9350 4500 8900 4500
|
||||
Connection ~ 8900 4300
|
||||
Connection ~ 8900 3600
|
||||
Connection ~ 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 9350 4300
|
||||
Wire Wire Line
|
||||
9650 4800 9650 5050
|
||||
Wire Wire Line
|
||||
9350 3600 8900 3600
|
||||
Wire Wire Line
|
||||
9050 3700 9350 3700
|
||||
Wire Wire Line
|
||||
8900 3800 9350 3800
|
||||
Wire Wire Line
|
||||
8900 4000 9350 4000
|
||||
Wire Wire Line
|
||||
8900 3800 8900 4000
|
||||
Connection ~ 8900 3800
|
||||
Wire Wire Line
|
||||
8900 3600 8900 3800
|
||||
NoConn ~ 9350 4200
|
||||
NoConn ~ 9950 4500
|
||||
NoConn ~ 9950 3900
|
||||
Text Label 2150 3700 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 2150 4600 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 2150 4000 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 2150 3800 0 50 ~ 0
|
||||
CS
|
||||
Text Label 2150 3600 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
7550 4450 7200 4450
|
||||
Wire Wire Line
|
||||
7550 4800 7200 4800
|
||||
Text Label 7950 4800 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 7950 4450 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
7850 4800 8200 4800
|
||||
Wire Wire Line
|
||||
7850 4450 8200 4450
|
||||
$Comp
|
||||
L Diode:1N4148 D3
|
||||
U 1 1 615851AF
|
||||
P 7700 4450
|
||||
F 0 "D3" H 7700 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4576 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4450 50 0001 C CNN
|
||||
1 7700 4450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2100 4600 2400 4600
|
||||
Wire Wire Line
|
||||
2100 4000 2400 4000
|
||||
Wire Wire Line
|
||||
2100 3800 2400 3800
|
||||
Wire Wire Line
|
||||
2100 3600 2400 3600
|
||||
Wire Wire Line
|
||||
2100 4700 2400 4700
|
||||
Wire Wire Line
|
||||
2100 4500 2400 4500
|
||||
Wire Wire Line
|
||||
2100 3900 2400 3900
|
||||
Wire Wire Line
|
||||
2100 3700 2400 3700
|
||||
Wire Wire Line
|
||||
1800 5050 1800 5000
|
||||
Text Label 7950 4050 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 7950 3700 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
7850 4050 8200 4050
|
||||
Wire Wire Line
|
||||
7850 3700 8200 3700
|
||||
$Comp
|
||||
L Diode:1N4148 D5
|
||||
U 1 1 61587AEA
|
||||
P 7700 3700
|
||||
F 0 "D5" H 7700 3917 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 3826 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 3525 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 3700 50 0001 C CNN
|
||||
1 7700 3700
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D6
|
||||
U 1 1 615862A9
|
||||
P 7700 4050
|
||||
F 0 "D6" H 7700 4267 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4176 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 3875 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4050 50 0001 C CNN
|
||||
1 7700 4050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D4
|
||||
U 1 1 6158496F
|
||||
P 7700 4800
|
||||
F 0 "D4" H 7700 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4926 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4800 50 0001 C CNN
|
||||
1 7700 4800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2800 4350 3150 4350
|
||||
Text Label 3100 4350 2 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
2800 4450 3150 4450
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4450
|
||||
Wire Wire Line
|
||||
4050 4450 3750 4450
|
||||
Connection ~ 4050 4350
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4250
|
||||
Connection ~ 4050 4250
|
||||
Wire Wire Line
|
||||
4050 4250 3750 4250
|
||||
Wire Wire Line
|
||||
4050 4250 4050 4150
|
||||
Wire Wire Line
|
||||
4050 4150 3750 4150
|
||||
Text Label 9100 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4300 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3600 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3800 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4000 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 4300 2400 4300
|
||||
Text Label 2150 3400 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:Mac_DB15_Male_MountingHoles J1
|
||||
U 1 1 6154A803
|
||||
P 1800 4100
|
||||
F 0 "J1" H 1894 5092 50 0000 C CNN
|
||||
F 1 "Mac_DB15_Male_MountingHoles" H 1894 5001 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm" H 1800 4100 50 0001 C CNN
|
||||
F 3 " ~" H 1800 4100 50 0001 C CNN
|
||||
1 1800 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 2150 4300 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:VGA_DB15_Female_HighDensity_MountingHoles J2
|
||||
U 1 1 6151FC86
|
||||
P 9650 4100
|
||||
F 0 "J2" H 9650 4967 50 0000 C CNN
|
||||
F 1 "VGA_DB15_Female_HighDensity_MountingHoles" H 9650 4876 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm" H 8700 4500 50 0001 C CNN
|
||||
F 3 " ~" H 8700 4500 50 0001 C CNN
|
||||
1 9650 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 9100 3700 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
5900 4050 5550 4050
|
||||
Text Label 10000 3700 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 3900 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4400 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4200 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
9350 3900 9050 3900
|
||||
Text Label 9100 3900 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
2100 4400 2400 4400
|
||||
Text Label 2150 4400 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3500 2400 3500
|
||||
Text Label 2150 3500 0 50 ~ 0
|
||||
B
|
||||
Wire Wire Line
|
||||
9350 4100 9050 4100
|
||||
Text Label 9100 4100 0 50 ~ 0
|
||||
B
|
||||
$Comp
|
||||
L Diode:1N4148 D1
|
||||
U 1 1 61582C6F
|
||||
P 4750 4450
|
||||
F 0 "D1" H 4750 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4576 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 4750 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4450 50 0001 C CNN
|
||||
1 4750 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 3100 4150 2 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
2800 4150 3150 4150
|
||||
Text Label 3100 4250 2 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
2800 4250 3150 4250
|
||||
Wire Wire Line
|
||||
2800 4050 3150 4050
|
||||
Wire Wire Line
|
||||
5900 3950 5550 3950
|
||||
Wire Wire Line
|
||||
5550 3950 5550 4050
|
||||
Wire Wire Line
|
||||
2100 4100 2400 4100
|
||||
Text Label 2150 4100 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4050 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4450 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3400 8900 3400
|
||||
Wire Wire Line
|
||||
5550 3850 5900 3850
|
||||
Text Label 5650 3850 0 50 ~ 0
|
||||
CS
|
||||
Text Label 5650 4450 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
5550 4450 5900 4450
|
||||
Wire Wire Line
|
||||
5550 4350 5900 4350
|
||||
Wire Wire Line
|
||||
5550 4350 5550 4450
|
||||
Wire Wire Line
|
||||
8200 3700 8200 4050
|
||||
Wire Wire Line
|
||||
8200 4450 8200 4800
|
||||
Wire Wire Line
|
||||
2100 4200 2400 4200
|
||||
Wire Wire Line
|
||||
5200 4450 5200 4800
|
||||
Wire Wire Line
|
||||
5900 4250 5550 4250
|
||||
Wire Wire Line
|
||||
5550 4150 5900 4150
|
||||
Text Label 2150 4700 0 50 ~ 0
|
||||
HS
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWB1
|
||||
U 1 1 6152990A
|
||||
P 6200 4050
|
||||
F 0 "SWB1" H 6200 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 6200 4626 50 0000 C CNN
|
||||
F 2 "project:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" H 6200 4050 50 0001 C CNN
|
||||
F 3 "~" H 6200 4050 50 0001 C CNN
|
||||
1 6200 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5900 3750 5550 3750
|
||||
Text Label 5650 3750 0 50 ~ 0
|
||||
HS
|
||||
Wire Wire Line
|
||||
6500 3750 6900 3750
|
||||
Wire Wire Line
|
||||
9950 4100 10250 4100
|
||||
Text Label 10000 4100 0 50 ~ 0
|
||||
HS-CS
|
||||
Wire Wire Line
|
||||
3750 4050 4050 4050
|
||||
Text Label 3800 4050 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
9950 4300 10250 4300
|
||||
Text Label 10000 4300 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
6500 4450 6900 4450
|
||||
Wire Wire Line
|
||||
6500 4350 6900 4350
|
||||
Text Label 4450 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 4450 4800 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4350 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 7350 4800 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
6500 4250 6900 4250
|
||||
Text Label 6600 4250 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
7550 3700 7200 3700
|
||||
Wire Wire Line
|
||||
7550 4050 7200 4050
|
||||
Wire Wire Line
|
||||
6500 4150 6900 4150
|
||||
Text Label 6600 4150 0 50 ~ 0
|
||||
D3
|
||||
Text Label 7350 4450 0 50 ~ 0
|
||||
D3
|
||||
Wire Wire Line
|
||||
6500 4050 6900 4050
|
||||
Wire Wire Line
|
||||
6500 3950 6900 3950
|
||||
Text Label 6600 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 3700 0 50 ~ 0
|
||||
D5
|
||||
Wire Wire Line
|
||||
6500 3850 6900 3850
|
||||
Wire Wire Line
|
||||
6900 3850 6900 3750
|
||||
Text Label 6600 3950 0 50 ~ 0
|
||||
D5
|
||||
Text Label 6600 3850 0 50 ~ 0
|
||||
HS-CS
|
||||
Text Notes 7050 6700 0 50 ~ 0
|
||||
Sony MacView / Unimac 82D Schematics
|
||||
Text Notes 7050 6800 0 50 ~ 0
|
||||
CC BY-NC-SA 4.0
|
||||
Text Notes 7400 7500 0 50 ~ 0
|
||||
DB-15 to VGA TH v1.0
|
||||
Text Notes 8150 7650 0 50 ~ 0
|
||||
November 18, 2021
|
||||
Wire Wire Line
|
||||
1800 5050 9650 5050
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWA1
|
||||
U 1 1 61528095
|
||||
P 3450 4050
|
||||
F 0 "SWA1" H 3450 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 3450 4626 50 0000 C CNN
|
||||
F 2 "project:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" H 3450 4050 50 0001 C CNN
|
||||
F 3 "~" H 3450 4050 50 0001 C CNN
|
||||
1 3450 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
NoConn ~ 3750 3750
|
||||
NoConn ~ 3750 3850
|
||||
NoConn ~ 3750 3950
|
||||
NoConn ~ 3150 3950
|
||||
NoConn ~ 3150 3850
|
||||
NoConn ~ 3150 3750
|
||||
$EndSCHEMATC
|
||||
3383
kicad/Mac DB15 to VGA TH v1.2.kicad_pcb
Normal file
3383
kicad/Mac DB15 to VGA TH v1.2.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
251
kicad/Mac DB15 to VGA TH v1.2.pro
Normal file
251
kicad/Mac DB15 to VGA TH v1.2.pro
Normal file
@ -0,0 +1,251 @@
|
||||
update=1/26/2022 3:39:52 PM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=Mac DB-15 to VGA TH v1.0.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=0
|
||||
MinTrackWidth=0.127
|
||||
MinViaDiameter=0.6
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.127
|
||||
TrackWidth2=0.5
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.05
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.127
|
||||
TrackWidth=0.127
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
427
kicad/Mac DB15 to VGA TH v1.2.sch
Normal file
427
kicad/Mac DB15 to VGA TH v1.2.sch
Normal file
@ -0,0 +1,427 @@
|
||||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Diode:1N4148 D2
|
||||
U 1 1 61588880
|
||||
P 4750 4800
|
||||
F 0 "D2" H 4750 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4926 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 4750 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4800 50 0001 C CNN
|
||||
1 4750 4800
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3750 4350 4050 4350
|
||||
Wire Wire Line
|
||||
4900 4450 5200 4450
|
||||
Wire Wire Line
|
||||
4900 4800 5200 4800
|
||||
Text Label 4950 4450 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 4950 4800 0 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
4600 4800 4300 4800
|
||||
Wire Wire Line
|
||||
4600 4450 4300 4450
|
||||
Text Label 5650 4050 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
5550 4250 5550 4150
|
||||
Text Label 5650 4250 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 9100 5050 0 50 ~ 0
|
||||
GND.S
|
||||
Wire Wire Line
|
||||
9350 4400 9050 4400
|
||||
Wire Wire Line
|
||||
8900 3400 8900 3600
|
||||
Wire Wire Line
|
||||
9950 3700 10250 3700
|
||||
Wire Wire Line
|
||||
8900 4500 8900 4300
|
||||
Wire Wire Line
|
||||
9350 4500 8900 4500
|
||||
Connection ~ 8900 4300
|
||||
Connection ~ 8900 3600
|
||||
Connection ~ 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 9350 4300
|
||||
Wire Wire Line
|
||||
9650 4800 9650 5050
|
||||
Wire Wire Line
|
||||
9350 3600 8900 3600
|
||||
Wire Wire Line
|
||||
9050 3700 9350 3700
|
||||
Wire Wire Line
|
||||
8900 3800 9350 3800
|
||||
Wire Wire Line
|
||||
8900 4000 9350 4000
|
||||
Wire Wire Line
|
||||
8900 3800 8900 4000
|
||||
Connection ~ 8900 3800
|
||||
Wire Wire Line
|
||||
8900 3600 8900 3800
|
||||
NoConn ~ 9350 4200
|
||||
NoConn ~ 9950 4500
|
||||
NoConn ~ 9950 3900
|
||||
Text Label 2150 3700 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 2150 4600 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 2150 4000 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 2150 3800 0 50 ~ 0
|
||||
CS
|
||||
Text Label 2150 3600 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
7550 4450 7200 4450
|
||||
Wire Wire Line
|
||||
7550 4800 7200 4800
|
||||
Text Label 7950 4800 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 7950 4450 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
7850 4800 8200 4800
|
||||
Wire Wire Line
|
||||
7850 4450 8200 4450
|
||||
$Comp
|
||||
L Diode:1N4148 D3
|
||||
U 1 1 615851AF
|
||||
P 7700 4450
|
||||
F 0 "D3" H 7700 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4576 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4450 50 0001 C CNN
|
||||
1 7700 4450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2100 4600 2400 4600
|
||||
Wire Wire Line
|
||||
2100 4000 2400 4000
|
||||
Wire Wire Line
|
||||
2100 3800 2400 3800
|
||||
Wire Wire Line
|
||||
2100 3600 2400 3600
|
||||
Wire Wire Line
|
||||
2100 4700 2400 4700
|
||||
Wire Wire Line
|
||||
2100 4500 2400 4500
|
||||
Wire Wire Line
|
||||
2100 3900 2400 3900
|
||||
Wire Wire Line
|
||||
2100 3700 2400 3700
|
||||
Wire Wire Line
|
||||
1800 5050 1800 5000
|
||||
Text Label 7950 4050 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 7950 3700 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
7850 4050 8200 4050
|
||||
Wire Wire Line
|
||||
7850 3700 8200 3700
|
||||
$Comp
|
||||
L Diode:1N4148 D5
|
||||
U 1 1 61587AEA
|
||||
P 7700 3700
|
||||
F 0 "D5" H 7700 3917 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 3826 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 3525 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 3700 50 0001 C CNN
|
||||
1 7700 3700
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D6
|
||||
U 1 1 615862A9
|
||||
P 7700 4050
|
||||
F 0 "D6" H 7700 4267 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4176 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 3875 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4050 50 0001 C CNN
|
||||
1 7700 4050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D4
|
||||
U 1 1 6158496F
|
||||
P 7700 4800
|
||||
F 0 "D4" H 7700 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4926 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4800 50 0001 C CNN
|
||||
1 7700 4800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2800 4350 3150 4350
|
||||
Text Label 3100 4350 2 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
2800 4450 3150 4450
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4450
|
||||
Wire Wire Line
|
||||
4050 4450 3750 4450
|
||||
Connection ~ 4050 4350
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4250
|
||||
Connection ~ 4050 4250
|
||||
Wire Wire Line
|
||||
4050 4250 3750 4250
|
||||
Wire Wire Line
|
||||
4050 4250 4050 4150
|
||||
Wire Wire Line
|
||||
4050 4150 3750 4150
|
||||
Text Label 9100 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4300 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3600 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3800 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4000 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 4300 2400 4300
|
||||
Text Label 2150 3400 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:Mac_DB15_Male_MountingHoles J1
|
||||
U 1 1 6154A803
|
||||
P 1800 4100
|
||||
F 0 "J1" H 1894 5092 50 0000 C CNN
|
||||
F 1 "Mac_DB15_Male_MountingHoles" H 1894 5001 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm" H 1800 4100 50 0001 C CNN
|
||||
F 3 " ~" H 1800 4100 50 0001 C CNN
|
||||
1 1800 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 2150 4300 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:VGA_DB15_Female_HighDensity_MountingHoles J2
|
||||
U 1 1 6151FC86
|
||||
P 9650 4100
|
||||
F 0 "J2" H 9650 4967 50 0000 C CNN
|
||||
F 1 "VGA_DB15_Female_HighDensity_MountingHoles" H 9650 4876 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm" H 8700 4500 50 0001 C CNN
|
||||
F 3 " ~" H 8700 4500 50 0001 C CNN
|
||||
1 9650 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 9100 3700 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
5900 4050 5550 4050
|
||||
Text Label 10000 3700 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 3900 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4400 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4200 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
9350 3900 9050 3900
|
||||
Text Label 9100 3900 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
2100 4400 2400 4400
|
||||
Text Label 2150 4400 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3500 2400 3500
|
||||
Text Label 2150 3500 0 50 ~ 0
|
||||
B
|
||||
Wire Wire Line
|
||||
9350 4100 9050 4100
|
||||
Text Label 9100 4100 0 50 ~ 0
|
||||
B
|
||||
$Comp
|
||||
L Diode:1N4148 D1
|
||||
U 1 1 61582C6F
|
||||
P 4750 4450
|
||||
F 0 "D1" H 4750 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4576 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 4750 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4450 50 0001 C CNN
|
||||
1 4750 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 3100 4150 2 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
2800 4150 3150 4150
|
||||
Text Label 3100 4250 2 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
2800 4250 3150 4250
|
||||
Wire Wire Line
|
||||
2800 4050 3150 4050
|
||||
Wire Wire Line
|
||||
5900 3950 5550 3950
|
||||
Wire Wire Line
|
||||
5550 3950 5550 4050
|
||||
Wire Wire Line
|
||||
2100 4100 2400 4100
|
||||
Text Label 2150 4100 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4050 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4450 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3400 8900 3400
|
||||
Wire Wire Line
|
||||
5550 3850 5900 3850
|
||||
Text Label 5650 3850 0 50 ~ 0
|
||||
CS
|
||||
Text Label 5650 4450 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
5550 4450 5900 4450
|
||||
Wire Wire Line
|
||||
5550 4350 5900 4350
|
||||
Wire Wire Line
|
||||
5550 4350 5550 4450
|
||||
Wire Wire Line
|
||||
8200 3700 8200 4050
|
||||
Wire Wire Line
|
||||
8200 4450 8200 4800
|
||||
Wire Wire Line
|
||||
2100 4200 2400 4200
|
||||
Wire Wire Line
|
||||
5200 4450 5200 4800
|
||||
Wire Wire Line
|
||||
5900 4250 5550 4250
|
||||
Wire Wire Line
|
||||
5550 4150 5900 4150
|
||||
Text Label 2150 4700 0 50 ~ 0
|
||||
HS
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWB1
|
||||
U 1 1 6152990A
|
||||
P 6200 4050
|
||||
F 0 "SWB1" H 6200 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 6200 4626 50 0000 C CNN
|
||||
F 2 "project:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" H 6200 4050 50 0001 C CNN
|
||||
F 3 "~" H 6200 4050 50 0001 C CNN
|
||||
1 6200 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5900 3750 5550 3750
|
||||
Text Label 5650 3750 0 50 ~ 0
|
||||
HS
|
||||
Wire Wire Line
|
||||
6500 3750 6900 3750
|
||||
Wire Wire Line
|
||||
9950 4100 10250 4100
|
||||
Text Label 10000 4100 0 50 ~ 0
|
||||
HS-CS
|
||||
Wire Wire Line
|
||||
3750 4050 4050 4050
|
||||
Text Label 3800 4050 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
9950 4300 10250 4300
|
||||
Text Label 10000 4300 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
6500 4450 6900 4450
|
||||
Wire Wire Line
|
||||
6500 4350 6900 4350
|
||||
Text Label 4450 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 4450 4800 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4350 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 7350 4800 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
6500 4250 6900 4250
|
||||
Text Label 6600 4250 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
7550 3700 7200 3700
|
||||
Wire Wire Line
|
||||
7550 4050 7200 4050
|
||||
Wire Wire Line
|
||||
6500 4150 6900 4150
|
||||
Text Label 6600 4150 0 50 ~ 0
|
||||
D3
|
||||
Text Label 7350 4450 0 50 ~ 0
|
||||
D3
|
||||
Wire Wire Line
|
||||
6500 4050 6900 4050
|
||||
Wire Wire Line
|
||||
6500 3950 6900 3950
|
||||
Text Label 6600 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 3700 0 50 ~ 0
|
||||
D5
|
||||
Wire Wire Line
|
||||
6500 3850 6900 3850
|
||||
Wire Wire Line
|
||||
6900 3850 6900 3750
|
||||
Text Label 6600 3950 0 50 ~ 0
|
||||
D5
|
||||
Text Label 6600 3850 0 50 ~ 0
|
||||
HS-CS
|
||||
Text Notes 7050 6700 0 50 ~ 0
|
||||
Sony MacView / Unimac 82D Schematics
|
||||
Text Notes 7050 6800 0 50 ~ 0
|
||||
CC BY-NC-SA 4.0
|
||||
Text Notes 7400 7500 0 50 ~ 0
|
||||
DB-15 to VGA TH v1.0
|
||||
Text Notes 8150 7650 0 50 ~ 0
|
||||
November 18, 2021
|
||||
Wire Wire Line
|
||||
1800 5050 9650 5050
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWA1
|
||||
U 1 1 61528095
|
||||
P 3450 4050
|
||||
F 0 "SWA1" H 3450 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 3450 4626 50 0000 C CNN
|
||||
F 2 "project:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" H 3450 4050 50 0001 C CNN
|
||||
F 3 "~" H 3450 4050 50 0001 C CNN
|
||||
1 3450 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
NoConn ~ 3750 3750
|
||||
NoConn ~ 3750 3850
|
||||
NoConn ~ 3750 3950
|
||||
NoConn ~ 3150 3950
|
||||
NoConn ~ 3150 3850
|
||||
NoConn ~ 3150 3750
|
||||
$EndSCHEMATC
|
||||
Loading…
x
Reference in New Issue
Block a user