Migrate to KiCAD 6

This commit is contained in:
Zane Kaminski 2022-03-26 06:02:46 -04:00
parent 93bf55767e
commit b66eaa9825
19 changed files with 181588 additions and 49743 deletions

2
.gitignore vendored
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@ -14,6 +14,7 @@ _autosave-*
*-save.pro
*-save.kicad_pcb
fp-info-cache
NuBus-ESP32-backups/*
# Netlist files (exported from Eeschema)
*.net
@ -27,3 +28,4 @@ cpld/db/GR8RAM.db_info
cpld/db/GR8RAM.tmw_info
cpld/GR8RAM.qws
Documentation/~$4205AManual.docx
NuBus-ESP32.kicad_prl

1489
AddrLatch.kicad_sch Normal file

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@ -1,558 +0,0 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 8 8
Title "NuBus-ESP32"
Date "2021-11-18"
Rev "0.1"
Comp "Garrett's Workshop"
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Comment2 ""
Comment3 ""
Comment4 ""
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L~A~11
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~AD~21
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~AD~20
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~AD~19
Text Label 4000 1950 2 50 ~ 0
~AD~18
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~AD~17
Text Label 4000 2150 2 50 ~ 0
~AD~16
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~AD~8
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~AD~15
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~AD~14
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~AD~13
Text Label 4000 2950 2 50 ~ 0
~AD~12
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~AD~11
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~AD~10
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Wire Wire Line
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Wire Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Wire Wire Line
4000 2150 3800 2150
Wire Wire Line
4000 2050 3800 2050
Wire Wire Line
4000 1950 3800 1950
Wire Wire Line
4000 1850 3800 1850
Wire Wire Line
4000 1750 3800 1750
Wire Wire Line
4000 1650 3800 1650
Wire Wire Line
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Wire Bus Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Wire Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 5200 4850
Wire Wire Line
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Wire Wire Line
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F 3 "" H 4400 4500 60 0001 C CNN
F 4 "C6097" H 4400 4400 50 0001 C CNN "LCSC Part"
1 4400 4400
1 0 0 -1
$EndComp
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AR Path="/61C6168C/620FC63C" Ref="C?" Part="1"
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F 3 "~" H 6500 3200 50 0001 C CNN
F 4 "C15850" H 6500 3200 50 0001 C CNN "LCSC Part"
1 6500 3200
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 620FC648
P 6900 3300
AR Path="/620FC648" Ref="#PWR?" Part="1"
AR Path="/61C8B24A/620FC648" Ref="#PWR0196" Part="1"
F 0 "#PWR0196" H 6900 3050 50 0001 C CNN
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F 3 "" H 6900 3300 50 0001 C CNN
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$Comp
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AR Path="/620FC65A" Ref="C?" Part="1"
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$EndComp
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Connection ~ 6500 3300
Wire Wire Line
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Connection ~ 6500 3100
Wire Wire Line
6500 3100 6100 3100
Wire Wire Line
6900 3100 6500 3100
Connection ~ 6900 3300
Connection ~ 4000 3650
Wire Wire Line
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Wire Wire Line
4800 3450 5000 3450
Wire Wire Line
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Text Label 4800 3550 0 50 ~ 0
L~A~6
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Connection ~ 4000 2450
$Comp
L power:+3V3 #PWR0122
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1 6100 3100
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$EndComp
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$Comp
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$Comp
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$Comp
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F 3 "" H 4000 4850 50 0001 C CNN
1 4000 4850
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Wire Bus Line
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~TM~0
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Wire Wire Line
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3700 4550 3800 4650
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~AD~0
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3700 4450 3800 4550
Wire Wire Line
4000 4550 3800 4550
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L~A~0
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Entry Wire Line
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L~TM~0
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Entry Wire Line
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Text Label 4800 4650 0 50 ~ 0
L~TM~1
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~AD~1
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Text Label 4800 4450 0 50 ~ 0
L~A~1
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Entry Wire Line
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Wire Bus Line
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Wire Bus Line
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$EndSCHEMATC

4584
BusControl.kicad_sch Normal file

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File diff suppressed because it is too large Load Diff

1981
CtrlStatReg.kicad_sch Normal file

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@ -1,663 +0,0 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 8
Title "NuBus-ESP32"
Date "2021-11-18"
Rev "0.1"
Comp "Garrett's Workshop"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
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1000 5400 1900 5400
$Comp
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AR Path="/64084316/61A765AC" Ref="#PWR?" Part="1"
AR Path="/61CA157A/61A765AC" Ref="#PWR0213" Part="1"
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F 3 "" H 9150 5000 50 0001 C CNN
1 9150 5000
1 0 0 -1
$EndComp
$Comp
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AR Path="/61A765B2" Ref="C?" Part="1"
AR Path="/64084316/61A765B2" Ref="C?" Part="1"
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F 3 "~" H 9150 5100 50 0001 C CNN
F 4 "C15850" H 9150 5100 50 0001 C CNN "LCSC Part"
1 9150 5100
-1 0 0 -1
$EndComp
$Comp
L Device:C_Small C?
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P 9550 5100
AR Path="/61A765B8" Ref="C?" Part="1"
AR Path="/64084316/61A765B8" Ref="C?" Part="1"
AR Path="/61CA157A/61A765B8" Ref="C44" Part="1"
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F 1 "10u" H 9458 5055 50 0000 R CNN
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F 3 "~" H 9550 5100 50 0001 C CNN
F 4 "C15850" H 9550 5100 50 0001 C CNN "LCSC Part"
1 9550 5100
-1 0 0 -1
$EndComp
$Comp
L Device:C_Small C?
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AR Path="/61A765BE" Ref="C?" Part="1"
AR Path="/64084316/61A765BE" Ref="C?" Part="1"
AR Path="/61CA157A/61A765BE" Ref="C45" Part="1"
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1 9950 5100
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
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P 9950 5200
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AR Path="/61CA157A/61A765C4" Ref="#PWR0214" Part="1"
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F 1 "GND" H 9950 5050 50 0000 C CNN
F 2 "" H 9950 5200 50 0001 C CNN
F 3 "" H 9950 5200 50 0001 C CNN
1 9950 5200
1 0 0 -1
$EndComp
Wire Wire Line
9550 5000 9150 5000
Wire Wire Line
9550 5000 9950 5000
Connection ~ 9550 5000
Wire Wire Line
9950 5200 9550 5200
Connection ~ 9950 5200
Connection ~ 9550 5200
Wire Wire Line
9550 5200 9150 5200
Connection ~ 9150 5000
Wire Wire Line
4050 5100 4150 5100
Wire Wire Line
4150 3300 4050 3300
Wire Wire Line
4450 3050 4650 3050
Wire Wire Line
3850 3050 3550 3050
Wire Wire Line
3750 2350 4850 2350
Wire Wire Line
4850 1450 3550 1450
Text HLabel 2550 4050 0 50 Input ~ 0
RDCLK
Wire Wire Line
2550 4050 2950 4050
Wire Wire Line
2950 3750 2950 3950
Wire Wire Line
3250 3750 2950 3750
$Comp
L power:+3V3 #PWR?
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P 3250 3750
AR Path="/61C6168C/682B83B0" Ref="#PWR?" Part="1"
AR Path="/61CA157A/682B83B0" Ref="#PWR0212" Part="1"
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F 3 "" H 3250 3750 50 0001 C CNN
1 3250 3750
1 0 0 -1
$EndComp
Text Notes 1050 2300 0 50 ~ 0
Write request\nfrom Mac to ESP32
Wire Notes Line
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Text Notes 1050 3200 0 50 ~ 0
Pending bit registered\nfor readback by Mac
Wire Notes Line
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Text Notes 1050 5000 0 50 ~ 0
Pending bit registered\nfor readback by Mac
Wire Notes Line
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Text Notes 1050 4100 0 50 ~ 0
Read request\nfrom ESP32 to Mac
Wire Notes Line
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Text Notes 1050 1400 0 50 ~ 0
ESP32 reset bit
Wire Notes Line
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Wire Wire Line
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Wire Wire Line
2850 2000 2950 2000
Wire Wire Line
4850 4150 3750 4150
Connection ~ 3750 4150
Text Label 3850 4850 2 50 ~ 0
~RDREQ~N
$Comp
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F 2 "" H 2850 2000 50 0001 C CNN
F 3 "" H 2850 2000 50 0001 C CNN
1 2850 2000
1 0 0 -1
$EndComp
Wire Wire Line
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Text HLabel 4050 3300 0 50 Input ~ 0
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AR Path="/61CA157A/679639E3" Ref="#PWR0209" Part="1"
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F 3 "" H 2950 3450 50 0001 C CNN
1 2950 3450
1 0 0 -1
$EndComp
$Comp
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U 1 1 679639DD
P 3250 2850
AR Path="/61C6168C/679639DD" Ref="#PWR?" Part="1"
AR Path="/61CA157A/679639DD" Ref="#PWR0208" Part="1"
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F 2 "" H 3250 2850 50 0001 C CNN
F 3 "" H 3250 2850 50 0001 C CNN
1 3250 2850
1 0 0 -1
$EndComp
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Entry Wire Line
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~AD~[31..0]
Text Label 4450 3050 0 50 ~ 0
~AD~22
Text Label 3850 3050 2 50 ~ 0
~WRREQ~N
NoConn ~ 3550 3250
Wire Wire Line
2950 3450 3250 3450
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
3750 2350 3550 2350
Connection ~ 3750 2350
Wire Wire Line
3750 2650 2850 2650
Wire Wire Line
3750 2350 3750 2650
Text HLabel 2550 3150 0 50 Input ~ 0
CLK
Text HLabel 2550 1950 0 50 Input ~ 0
REG~WE~
Wire Wire Line
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Text HLabel 4050 5100 0 50 Input ~ 0
ROM~OE~
$Comp
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$Comp
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5530
DataReg.kicad_sch Normal file

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2695
ESP32.kicad_sch Normal file

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1079
ESP32.sch

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479
NuBus-ESP32.kicad_pro Normal file
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@ -0,0 +1,479 @@
{
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"min_clearance": 0.15
}
},
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},
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"item_on_disabled_layer": "error",
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"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
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"zone_has_empty_net": "error",
"zones_intersect": "error"
},
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"rules": {
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{
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"layer_presets": []
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"boards": [],
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"meta": {
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"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
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"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
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"meta": {
"filename": "NuBus-ESP32.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "NuBus-ESP32.net",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 0.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Pcbnew",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"3a83a06c-b9a3-440b-8fa5-278e4d065348",
""
],
[
"00000000-0000-0000-0000-00006400a649",
"NuBus"
],
[
"00000000-0000-0000-0000-000061c6168c",
"DataReg"
],
[
"00000000-0000-0000-0000-000061ca157a",
"CtrlStatReg"
],
[
"00000000-0000-0000-0000-000061c8b24a",
"AddrLatch"
],
[
"00000000-0000-0000-0000-000062454aa9",
"ROM"
],
[
"00000000-0000-0000-0000-000061d1084d",
"BusControl"
],
[
"00000000-0000-0000-0000-000064084316",
"ESP32"
]
],
"text_variables": {}
}

3184
NuBus-ESP32.kicad_sch Normal file

File diff suppressed because it is too large Load Diff

View File

@ -1,265 +0,0 @@
update=Thursday, November 18, 2021 at 10:58:12 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=NuBus-ESP32.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.15
MinViaDiameter=0.5
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.15
TrackWidth2=0.2
TrackWidth3=0.25
TrackWidth4=0.3
TrackWidth5=0.35
TrackWidth6=0.4
TrackWidth7=0.45
TrackWidth8=0.5
TrackWidth9=0.6
TrackWidth10=0.7
TrackWidth11=0.8
TrackWidth12=1
ViaDiameter1=0.5
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
ViaDiameter4=1
ViaDrill4=0.5
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu