Here we show the desired cycle termination behavior on the NuBus. To be begin a transfer, a the Mac (or other NuBus master) drives /START low and puts valid data on the address bus and TM[1:0] transfer.
Notice how the NuBus clock has a 75% duty cycle. All signal transitions occur after the rising edge of CLK and all data is latched at the falling edge of CLK. The 75% duty cycle gives extra propagation delay and setup tiem after the clock rises before data is to be latched at the falling edge.
TM[1] high means write. TM[1] low means read. TM[0] and A[1:0] indicate the operation size and are not relevant for this application.
At each falling edge, NuBus slave devices check AD[31:28] and /START. If AD[31:28] matches the slave's card ID and /START is low, the card is supposed to recognize that a NuBus cycle has begun with the card as its target.
Once the slave device has completed the read/write operation, it responds with /ACK low and TM[1:0] high, indicating a successful transfer. Other values of TM[1:0] can be used to signal a bus error or retry condition. We aren't using those features.