2022-06-07 21:05:08 +00:00
|
|
|
#include "NuBusFPGARAMDskDrvr.h"
|
|
|
|
|
2022-10-08 16:23:01 +00:00
|
|
|
#ifdef ENABLE_DMA
|
2022-10-08 08:39:18 +00:00
|
|
|
OSErr changeRAMDskIRQ(AuxDCEPtr dce, char en, OSErr err) {
|
|
|
|
struct RAMDrvContext *ctx = *(struct RAMDrvContext**)dce->dCtlStorage;
|
|
|
|
|
|
|
|
if (en != ctx->irqen) {
|
|
|
|
/* write_reg(dce, GOBOFB_DEBUG, 0xBEEF0005); */
|
|
|
|
/* write_reg(dce, GOBOFB_DEBUG, en); */
|
|
|
|
|
|
|
|
if (en) {
|
|
|
|
if (SIntInstall(ctx->siqel, dce->dCtlSlot)) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (SIntRemove(ctx->siqel, dce->dCtlSlot)) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-10-08 16:23:01 +00:00
|
|
|
write_reg(dce, DMA_IRQ_CTL, en ? revb(0x3) : revb(0x2)); // 0x2: always clear pending interrupt
|
2022-10-08 08:39:18 +00:00
|
|
|
ctx->irqen = en;
|
|
|
|
}
|
|
|
|
return noErr;
|
|
|
|
}
|
2022-10-08 16:23:01 +00:00
|
|
|
#endif
|
2022-10-08 08:39:18 +00:00
|
|
|
|
|
|
|
|
2022-10-05 21:46:28 +00:00
|
|
|
#pragma parameter __D0 cNuBusFPGARAMDskCtl(__A0, __A1)
|
2022-06-07 21:05:08 +00:00
|
|
|
OSErr cNuBusFPGARAMDskCtl(CntrlParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
|
|
|
|
{
|
|
|
|
OSErr ret = noErr;
|
|
|
|
struct RAMDrvContext *ctx;
|
|
|
|
|
2022-06-26 10:31:43 +00:00
|
|
|
/* write_reg(dce, GOBOFB_DEBUG, 0xDEAD0002); */
|
|
|
|
/* write_reg(dce, GOBOFB_DEBUG, pb->csCode); */
|
2022-06-07 21:05:08 +00:00
|
|
|
|
|
|
|
ctx = *(struct RAMDrvContext**)dce->dCtlStorage;
|
|
|
|
|
|
|
|
if (ctx) {
|
|
|
|
switch (pb->csCode)
|
|
|
|
{
|
|
|
|
case kFormat:
|
|
|
|
ret = noErr;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = controlErr;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = offLinErr; /* r/w requested for an off-line drive */
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
done:
|
2022-10-05 20:41:27 +00:00
|
|
|
if (!(pb->ioTrap & (1<<noQueueBit)))
|
2022-10-06 21:28:07 +00:00
|
|
|
IODone((DCtlPtr)dce, ret);
|
2022-06-07 21:05:08 +00:00
|
|
|
return ret;
|
|
|
|
}
|