mirror of
https://github.com/rdolbeau/NuBusFPGA.git
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35 lines
1.1 KiB
Python
35 lines
1.1 KiB
Python
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from migen import *
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from migen.genlib.fifo import *
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import litex
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from litex.soc.interconnect import wishbone
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from migen.genlib.cdc import BusSynchronizer
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class NuBus2Wishbone(Module):
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"""Wishbone Clock Domain Crossing [Master]"""
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def __init__(self, nubus, wb):
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# memory
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# nubus.mem_valid
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# nubus.mem_addr
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# nubus.mem_wdata
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# nubus.mem_write
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# nubus.mem_ready
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# nubus.mem_rdata
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#nubus.mem_error
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#nubus.mem_tryagain
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self.comb += wb.cyc.eq(nubus.mem_valid)
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self.comb += wb.stb.eq(nubus.mem_valid)
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self.comb += If(nubus.mem_write == 0,
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wb.sel.eq(0xF)).Else(
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wb.sel.eq(nubus.mem_write))
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self.comb += wb.we.eq(nubus.mem_write != 0)
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self.comb += wb.adr.eq(Cat(nubus.mem_addr[2:24], Signal(8, reset = 0))) # 24 bits, a.k.a 22 bits of words
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self.comb += wb.dat_w.eq(nubus.mem_wdata)
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self.comb += nubus.mem_rdata.eq(wb.dat_r)
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self.comb += nubus.mem_ready.eq(wb.ack)
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self.comb += nubus.mem_error.eq(0)
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self.comb += nubus.mem_tryagain.eq(0)
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