mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-12-22 10:29:53 +00:00
46 lines
2.1 KiB
Python
46 lines
2.1 KiB
Python
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from migen import *
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from migen.genlib.fifo import *
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from migen.genlib.cdc import BusSynchronizer
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import litex
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from litex.soc.interconnect import wishbone
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class NuBusStat(Module):
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def __init__(self, nubus, platform):
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self.bus_slv = bus_slv = wishbone.Interface()
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read_ctr = Signal(32)
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writ_ctr = Signal(32)
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self.submodules.sync_read_ctr = BusSynchronizer(width = 32, idomain="nubus", odomain="sys")
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self.submodules.sync_writ_ctr = BusSynchronizer(width = 32, idomain="nubus", odomain="sys")
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self.comb += [
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self.sync_read_ctr.i.eq(nubus.read_ctr),
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read_ctr.eq(self.sync_read_ctr.o),
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self.sync_writ_ctr.i.eq(nubus.writ_ctr),
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writ_ctr.eq(self.sync_writ_ctr.o),
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]
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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wishbone_fsm.act("Reset",
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NextValue(bus_slv.ack, 0),
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NextState("Idle"))
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wishbone_fsm.act("Idle",
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If(bus_slv.cyc & bus_slv.stb & bus_slv.we & ~bus_slv.ack, #write
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# FIXME: should check for prefix?
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#Case(bus_slv.adr[0:10], {
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# 0x0: [ NextValue(read_ctr, bus_slv.dat_w[0:32]), ],
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# 0x1: [ NextValue(write_ctr, bus_slv.dat_w[0:32]), ],
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#}),
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NextValue(bus_slv.ack, 1),
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).Elif(bus_slv.cyc & bus_slv.stb & ~bus_slv.we & ~bus_slv.ack, #read
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Case(bus_slv.adr[0:10], {
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0x0: [ NextValue(bus_slv.dat_r, Cat(read_ctr[24:32], read_ctr[16:24], read_ctr[ 8:16], read_ctr[ 0: 8])), ],
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0x1: [ NextValue(bus_slv.dat_r, Cat(writ_ctr[24:32], writ_ctr[16:24], writ_ctr[ 8:16], writ_ctr[ 0: 8])), ],
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}),
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NextValue(bus_slv.ack, 1),
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).Else(
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NextValue(bus_slv.ack, 0),
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)
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)
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