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https://github.com/rdolbeau/NuBusFPGA.git
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support both version for now
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@ -108,7 +108,7 @@ class NuBus(Module):
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return "nubus"
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def add_sources(self, platform):
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platform.add_source("nubus.v", "verilog")
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platform.add_source("nubus_V1_0.v", "verilog")
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# XiBus is from my github, branch 'more_fixes'
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platform.add_source("/home/dolbeau/XiBus/nubus.svh", "verilog")
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#platform.add_source("/home/dolbeau/XiBus/nubus_arbiter.v", "verilog") # in the CPLD
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@ -169,7 +169,7 @@ class NuBus(Module):
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return "nubus"
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def add_sources(self, platform):
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platform.add_source("nubus.v", "verilog")
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platform.add_source("nubus_V1_2.v", "verilog")
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# XiBus is from my github, branch 'more_fixes'
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platform.add_source("XiBus/nubus.svh", "verilog")
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platform.add_source("nubus_arbiter.v", "verilog") # for CPLDinfpga
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@ -16,7 +16,6 @@ from litex.soc.cores.led import LedChaser
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import ztex213_nubus
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import nubus_to_fpga_export
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import nubus
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import nubus_full
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import nubus_full_sampling
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import nubus_stat
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@ -308,7 +307,11 @@ class NuBusFPGA(SoCCore):
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wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
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self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys)
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self.submodules.nubus = nubus.NuBus(platform=platform, cd_nubus="nubus")
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if (version == "V1.0"):
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from nubus_V1_0 import NuBus
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elif (version == "V1.2"):
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from nubus_V1_2 import NuBus
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self.submodules.nubus = NuBus(platform=platform, cd_nubus="nubus")
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#self.submodules.nubus2wishbone = ClockDomainsRenamer("nubus")(NuBus2Wishbone(nubus=self.nubus,wb=self.wishbone_master_nubus))
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if (version == "V1.2"):
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self.comb += self.nubus.nubus_oe.eq(hold_reset) # improveme
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