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NuBusFPGA
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support both version for now

This commit is contained in:
Romain Dolbeau 2022-11-01 15:42:59 +01:00
parent 4c2eb5f6d2
commit 036ce0a3ce
3 changed files with 7 additions and 4 deletions
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2
nubus-to-ztex-gateware/nubus_V1_0.py
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@ -108,7 +108,7 @@ class NuBus(Module):
return "nubus"
def add_sources(self, platform):
platform.add_source("nubus.v", "verilog")
platform.add_source("nubus_V1_0.v", "verilog")
# XiBus is from my github, branch 'more_fixes'
platform.add_source("/home/dolbeau/XiBus/nubus.svh", "verilog")
#platform.add_source("/home/dolbeau/XiBus/nubus_arbiter.v", "verilog") # in the CPLD

2
nubus-to-ztex-gateware/nubus_V1_2.py
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@ -169,7 +169,7 @@ class NuBus(Module):
return "nubus"
def add_sources(self, platform):
platform.add_source("nubus.v", "verilog")
platform.add_source("nubus_V1_2.v", "verilog")
# XiBus is from my github, branch 'more_fixes'
platform.add_source("XiBus/nubus.svh", "verilog")
platform.add_source("nubus_arbiter.v", "verilog") # for CPLDinfpga

7
nubus-to-ztex-gateware/nubus_to_fpga_soc.py
View File

@ -16,7 +16,6 @@ from litex.soc.cores.led import LedChaser
import ztex213_nubus
import nubus_to_fpga_export
import nubus
import nubus_full
import nubus_full_sampling
import nubus_stat
@ -308,7 +307,11 @@ class NuBusFPGA(SoCCore):
wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys)
self.submodules.nubus = nubus.NuBus(platform=platform, cd_nubus="nubus")
if (version == "V1.0"):
from nubus_V1_0 import NuBus
elif (version == "V1.2"):
from nubus_V1_2 import NuBus
self.submodules.nubus = NuBus(platform=platform, cd_nubus="nubus")
#self.submodules.nubus2wishbone = ClockDomainsRenamer("nubus")(NuBus2Wishbone(nubus=self.nubus,wb=self.wishbone_master_nubus))
if (version == "V1.2"):
self.comb += self.nubus.nubus_oe.eq(hold_reset) # improveme