diff --git a/.gitmodules b/.gitmodules
index f1cdecb..3af4d53 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,4 @@
 [submodule "nubus-to-ztex-gateware/XiBus"]
 	path = nubus-to-ztex-gateware/XiBus
 	url = git@github.com:rdolbeau/XiBus.git
+	branch = more_fixes
diff --git a/nubus-to-ztex-gateware/XiBus b/nubus-to-ztex-gateware/XiBus
index 44d7267..e20f6ca 160000
--- a/nubus-to-ztex-gateware/XiBus
+++ b/nubus-to-ztex-gateware/XiBus
@@ -1 +1 @@
-Subproject commit 44d7267ff802b54cebda7e0a643a90cff71247e4
+Subproject commit e20f6ca7c45900e841464b6bfd296a245093ca0a
diff --git a/nubus-to-ztex-gateware/nubus.py b/nubus-to-ztex-gateware/nubus.py
index 3ad6ffe..408d6d2 100644
--- a/nubus-to-ztex-gateware/nubus.py
+++ b/nubus-to-ztex-gateware/nubus.py
@@ -110,11 +110,11 @@ class NuBus(Module):
     def add_sources(self, platform):
         platform.add_source("nubus.v", "verilog")
         # XiBus is from my github, branch 'more_fixes'
-        platform.add_source("/home/dolbeau/XiBus/nubus.svh", "verilog")
-        #platform.add_source("/home/dolbeau/XiBus/nubus_arbiter.v", "verilog") # in the CPLD
-        platform.add_source("/home/dolbeau/XiBus/nubus_cpubus.v", "verilog")
-        platform.add_source("/home/dolbeau/XiBus/nubus_driver.v", "verilog")
-        #platform.add_source("/home/dolbeau/XiBus/nubus_errors.v", "verilog") # unused
-        platform.add_source("/home/dolbeau/XiBus/nubus_membus.v", "verilog")
-        platform.add_source("/home/dolbeau/XiBus/nubus_master.v", "verilog")
-        platform.add_source("/home/dolbeau/XiBus/nubus_slave.v", "verilog")
+        platform.add_source("XiBus/nubus.svh", "verilog")
+        #platform.add_source("XiBus/nubus_arbiter.v", "verilog") # in the CPLD
+        platform.add_source("XiBus/nubus_cpubus.v", "verilog")
+        platform.add_source("XiBus/nubus_driver.v", "verilog")
+        #platform.add_source("XiBus/nubus_errors.v", "verilog") # unused
+        platform.add_source("XiBus/nubus_membus.v", "verilog")
+        platform.add_source("XiBus/nubus_master.v", "verilog")
+        platform.add_source("XiBus/nubus_slave.v", "verilog")
diff --git a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py
index 5535131..2979d86 100644
--- a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py
+++ b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py
@@ -317,6 +317,14 @@ class NuBusFPGA(SoCCore):
             self.submodules.wishbone2nubus = ClockDomainsRenamer("nubus")(Wishbone2NuBus(nubus=self.nubus,wb=wishbone_slave_nubus))
             self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus")
             self.bus.add_slave("DMA", self.wishbone_slave_sys, SoCRegion(origin=self.mem_map.get("master", None), size=0x40000000, cached=False))
+            
+            irq_line = self.platform.request("nmrq_3v3_n") # active low
+            fb_irq = Signal() # active low
+            led0 = platform.request("user_led", 0)
+            self.comb += [
+                led0.eq(~fb_irq),
+            ]
+            self.comb += irq_line.eq(fb_irq) # active low, enable if one is low
         else:
             sampling = 1
             wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)