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https://github.com/rdolbeau/NuBusFPGA.git
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update ioRange; it doesn't actually affect the cache, only the MMU which we don't use...
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parent
972f628e80
commit
2d2cbdbafe
nubus-to-ztex-gateware
@ -60,7 +60,10 @@ object GenGoblinAccel { // extends App {
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),
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new StaticMemoryTranslatorPlugin(
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// only cache the sdram memory
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ioRange = addr => addr(31 downto 28) =/= 0x8
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ioRange = addr => ((addr(31 downto 28) =/= 0x8) & // SDRAM
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(addr(31 downto 12) =/= 0xF0902) & // SRAM
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(addr(31 downto 16) =/= 0xF091) // ROM
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)
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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@ -3493,7 +3493,7 @@ module VexRiscv (
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assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
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assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
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assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
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assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] != 4'b1000);
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assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] != 4'b1000) && (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 12] != 20'hf0902)) && (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 16] != 16'hf091));
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assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
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assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
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assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
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@ -3502,7 +3502,7 @@ module VexRiscv (
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assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
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assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
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assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
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assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] != 4'b1000);
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assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] != 4'b1000) && (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 12] != 20'hf0902)) && (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 16] != 16'hf091));
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assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
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assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
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assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
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