From 6271ddbef8c40afbc1de516ac52c71b2f6c01cdb Mon Sep 17 00:00:00 2001 From: Romain Dolbeau Date: Mon, 30 May 2022 19:06:33 +0200 Subject: [PATCH] pingmaster sort-of-work --- nubus-to-ztex-gateware/nubus_master_tst.py | 60 +++++++++++++-------- nubus-to-ztex-gateware/nubus_memfifo_wb.py | 8 +-- nubus-to-ztex-gateware/nubus_to_fpga_soc.py | 12 ++--- 3 files changed, 47 insertions(+), 33 deletions(-) diff --git a/nubus-to-ztex-gateware/nubus_master_tst.py b/nubus-to-ztex-gateware/nubus_master_tst.py index c9d75a6..0a4f3ce 100644 --- a/nubus-to-ztex-gateware/nubus_master_tst.py +++ b/nubus-to-ztex-gateware/nubus_master_tst.py @@ -5,22 +5,29 @@ import litex from litex.soc.interconnect import wishbone class PingMaster(Module): - def __init__(self): + def __init__(self, platform): self.bus_slv = bus_slv = wishbone.Interface() self.bus_mst = bus_mst = wishbone.Interface() + led0 = platform.request("user_led", 0) + led1 = platform.request("user_led", 1) + valu_reg = Signal(32) addr_reg = Signal(32) writ_del = Signal(6) - addr_reg_rev = Signal(32) + do_write = Signal() + #addr_reg_rev = Signal(32) + #self.comb += [ addr_reg_rev[ 0: 8].eq(addr_reg[24:32]), + # addr_reg_rev[ 8:16].eq(addr_reg[16:24]), + # addr_reg_rev[16:24].eq(addr_reg[ 8:16]), + # addr_reg_rev[24:32].eq(addr_reg[ 0: 8]), ] - self.comb += [ addr_reg_rev[ 0: 8].eq(addr_reg[24:32]), - addr_reg_rev[ 8:16].eq(addr_reg[16:24]), - addr_reg_rev[16:24].eq(addr_reg[ 8:16]), - addr_reg_rev[24:32].eq(addr_reg[ 0: 8]), ] - - self.sync += If(writ_del != 0, - writ_del.eq(writ_del - 1)) + self.sync += [ If(writ_del != 0, + writ_del.eq(writ_del - 1),), + If(writ_del == 1, + do_write.eq(1), + ) + ] self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset") wishbone_fsm.act("Reset", @@ -32,7 +39,7 @@ class PingMaster(Module): Case(bus_slv.adr[0:1], { 0x0: [ NextValue(valu_reg, bus_slv.dat_w[0:32]), ], 0x1: [ NextValue(addr_reg, bus_slv.dat_w[0:32]), - NextValue(writ_del, 3), ], + NextValue(writ_del, 63), ], }), NextValue(bus_slv.ack, 1), ).Elif(bus_slv.cyc & bus_slv.stb & ~bus_slv.we & ~bus_slv.ack, #read @@ -43,19 +50,26 @@ class PingMaster(Module): NextValue(bus_slv.ack, 1), ).Else( NextValue(bus_slv.ack, 0), - ), - If(writ_del == 1, - NextState("Write"),), - ) - wishbone_fsm.act("Write", - bus_mst.cyc.eq(1), - bus_mst.stb.eq(1), - bus_mst.we.eq(1), - bus_mst.dat_w.eq(valu_reg), - bus_mst.adr.eq(addr_reg[2:32]), - bus_mst.sel.eq(0xf), - If(bus_mst.ack, - NextState("Idle")), + ) ) + self.submodules.writer_fsm = writer_fsm = FSM(reset_state = "Reset") + writer_fsm.act("Reset", + NextState("Idle"),) + writer_fsm.act("Idle", + If(do_write, + NextValue(do_write, 0), + NextState("Write"),),) + writer_fsm.act("Write", + bus_mst.cyc.eq(1), + bus_mst.stb.eq(1), + bus_mst.we.eq(1), + bus_mst.dat_w.eq(valu_reg), + bus_mst.adr.eq(addr_reg[2:32]), + bus_mst.sel.eq(0xf), + If(bus_mst.ack, + NextState("Idle")), + ) + self.comb += [ led0.eq(bus_mst.cyc), + led1.eq(writ_del != 0), ] diff --git a/nubus-to-ztex-gateware/nubus_memfifo_wb.py b/nubus-to-ztex-gateware/nubus_memfifo_wb.py index 7851a69..2dcd2c1 100644 --- a/nubus-to-ztex-gateware/nubus_memfifo_wb.py +++ b/nubus-to-ztex-gateware/nubus_memfifo_wb.py @@ -59,10 +59,10 @@ class NuBus2WishboneFIFO(Module): self.comb += nubus.mem_error.eq(0) # FIXME: TODO: ??? self.comb += nubus.mem_tryagain.eq(0) # FIXME: TODO: ??? - led0 = platform.request("user_led", 0) - led1 = platform.request("user_led", 1) - self.comb += [ led0.eq(wb_read.ack), - led1.eq(write_ack), ] + #led0 = platform.request("user_led", 0) + #led1 = platform.request("user_led", 1) + #self.comb += [ led0.eq(wb_read.ack), + # led1.eq(write_ack), ] #self.submodules.write_fsm = write_fsm = FSM(reset_state = "Reset") #write_fsm.act("Reset", diff --git a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py index 9add9ea..2c3019a 100644 --- a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py +++ b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py @@ -255,8 +255,8 @@ class NuBusFPGA(SoCCore): "goblin_accel" : 0xF0901000, # accel for goblin (regs) "goblin_accel_ram" : 0xF0902000, # accel for goblin (scratch ram) "goblin_accel_rom" : 0xF0910000, # accel for goblin (rom) - "csr" : 0xF0a00000, # CSR - "pingmaster": 0xF0b00000, + "csr" : 0xF0A00000, # CSR + "pingmaster": 0xF0B00000, "rom": 0xF0FF8000, # ROM at the end (32 KiB of it ATM) #"END OF SLOT SPACE": 0xF0FFFFFF, } @@ -387,10 +387,10 @@ class NuBusFPGA(SoCCore): self.add_ram("goblin_accel_ram", origin=self.mem_map["goblin_accel_ram"], size=2**12, mode="rw") # for testing - #from nubus_master_tst import PingMaster - #self.submodules.pingmaster = PingMaster() - #self.bus.add_slave("pingmaster_slv", self.pingmaster.bus_slv, SoCRegion(origin=self.mem_map.get("pingmaster", None), size=0x010, cached=False)) - #self.bus.add_master(name="pingmaster_mst", master=self.pingmaster.bus_mst) + from nubus_master_tst import PingMaster + self.submodules.pingmaster = PingMaster(platform=self.platform) + self.bus.add_slave("pingmaster_slv", self.pingmaster.bus_slv, SoCRegion(origin=self.mem_map.get("pingmaster", None), size=0x010, cached=False)) + self.bus.add_master(name="pingmaster_mst", master=self.pingmaster.bus_mst) def main(): parser = argparse.ArgumentParser(description="SbusFPGA")