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accel in 16/32 ; includes adding MUL to Vex & fixing a FIFO overrun in NuBus in 32 bits mode

This commit is contained in:
Romain Dolbeau 2022-06-04 14:55:40 +02:00
parent 9a50f36153
commit 76c29d5b69
9 changed files with 2310 additions and 2021 deletions
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1
.gitignore vendored Normal file
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@ -0,0 +1 @@
**~

4
README.md
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@ -6,4 +6,6 @@ The goal of this repository is to be able to interface a modern (2021 era) [FPGA
## Current status
First prototype is working in a Quadra 650. It implements a basic single-resolution, depth-switchable (1/2/4/8/16/32 bits) unaccellerated framebuffer over HDMI. The framebuffer can be used as secondary/primary/only framebuffer in the machine running OS8.1. QEmu tests indicate this should work with 7.1 & 7.5/7.6 as well.
First prototype is working in a Quadra 650. It implements a basic single-resolution, depth-switchable (1/2/4/8/16/32 bits) framebuffer over HDMI. The framebuffer can be used as secondary/primary/only framebuffer in the machine running OS8.1. QEmu tests indicate this should work with 7.1 & 7.5/7.6 as well.
Some basic acceleration now exists for 8/16/32 bits, doing rectangle screen-to-screen blits and solid rectangle fills.

13
nubus-to-ztex-gateware/.gitignore vendored Normal file
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@ -0,0 +1,13 @@
*.log
*.orig
*.rej
*.BAK
*.jou
csr.csv
csr.json
blit
blit.o
blit.raw
blit.s
*.patch
OLD

80
nubus-to-ztex-gateware/NuBusFPGAInit/NuBusFPGAInit.c
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@ -28,38 +28,6 @@ void* fb_base;
void* bt_base;
void* accel_base;
#if 0
pascal void myStdBits(BitMap *srcBits, Rect *srcRect, Rect *dstRect, short mode, RgnHandle maskRgn){
long oldA4;
volatile unsigned long * const debug_ptr = (unsigned long*)0xFC90001c;
*debug_ptr = 0xC0FFEE00;
oldA4 = SetCurrentA4();
RememberA4();
oldStdBits(srcBits, srcRect, dstRect, mode, maskRgn);
SetA4(oldA4);
}
pascal void myBitBltX(BitMap *srcBits, BitMap *maskBits, BitMap *dstBits, Rect *srcRect, Rect *maskRect, Rect *dstRect, short mode, Pattern *pat, RgnHandle rgnA, RgnHandle rgnB, RgnHandle rgnC, short multColor){
register BitBltProc loldBitBlt;
register long oldA4;
volatile unsigned long * const debug_ptr = (unsigned long*)0xFC90001c;
*debug_ptr = 0xC0FFEE00;
oldA4 = SetCurrentA4();
RememberA4();
//oldBitBlt(srcBits, maskBits, dstBits, srcRect, maskRect, dstRect, mode, pat, rgnA, rgnB, rgnC, multColor);
loldBitBlt = oldBitBlt;
SetA4(oldA4);
loldBitBlt(srcBits, maskBits, dstBits, srcRect, maskRect, dstRect, mode, pat, rgnA, rgnB, rgnC, multColor);
}
#endif
static inline unsigned long brev(const unsigned long r) {
return (((r&0xFF000000)>>24) | ((r&0xFF0000)>>8) | ((r&0xFF00)<<8) | ((r&0xFF)<<24));
}
@ -442,6 +410,7 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
#endif
return 0;
}
if (srcpix->baseAddr != p_fb_base) { // we're not source
#ifdef QEMU
bt->debug = -5L;
@ -450,14 +419,6 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
return 0;
}
#if 0
if ((qdstack->MINRECT.top == 0x0) & (qdstack->MINRECT.bottom == 0x14) &
(qdstack->MINRECT.left == 0x5c9) & (qdstack->MINRECT.right == 0x5f6)) { // ignore that one until later
//*debug_ptr = -5L;
return 0;
}
#endif
{
Rect realrect, srcv, dstv;
short width = qdstack->MINRECT.right - qdstack->MINRECT.left;
@ -525,18 +486,18 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
#else
WAIT_FOR_HW_LE(accel_le);
accel_le->reg_width = (width);
accel_le->reg_width = (width << dstshift); // bytes
accel_le->reg_height = (height);
accel_le->reg_bitblt_dst_x = (dstv.left << dstshift);
accel_le->reg_bitblt_dst_x = (dstv.left << dstshift); // bytes
accel_le->reg_bitblt_dst_y = (dstv.top);
if (mode == 0) {
accel_le->reg_bitblt_src_x = (srcv.left << dstshift);
accel_le->reg_bitblt_src_x = (srcv.left << dstshift); // bytes
accel_le->reg_bitblt_src_y = (srcv.top);
accel_le->reg_cmd = (1<<DO_BLIT_BIT);
accel_le->reg_cmd = (1<<DO_BLIT_BIT);
} else if (mode == 8) {
accel_le->reg_fgcolor = (qdstack->EXPAT[0]);
accel_le->reg_cmd = (1<<DO_FILL_BIT);
accel_le->reg_cmd = (1<<DO_FILL_BIT);
}
WAIT_FOR_HW_LE(accel_le);
@ -597,18 +558,11 @@ pascal asm void myBitBlt(BitMap *srcBits, BitMap *maskBits, BitMap *dstBits, Rec
finish:
rts
}
//616 610
#if 0
CQDProcs customCProcs;
#endif
void main(void)
{
long oldA4;
#if 0
GrafPtr currPort;
#endif
Handle h;
struct goblin_bt_regs* bt;
@ -634,31 +588,13 @@ void main(void)
} else {
DebugStr("\pargh");
}
#if 0
GetPort(&currPort);
if (currPort->portBits.rowBytes < 0) /* color port */ {
SetStdCProcs(&customCProcs);
customCProcs.bitsProc = myStdBits;
currPort->grafProcs = (QDProcs*)&customCProcs;
*debug_ptr = 0;
} else {
*debug_ptr = 0xF00FF00F;
}
#endif
#if 0
oldStdBits = (StdBitsProc)GetToolTrapAddress(_StdBits);
*debug_ptr = (unsigned long)oldStdBits;
SetToolTrapAddress((UniversalProcPtr)myStdBits, _StdBits);
#endif
oldBitBlt = (BitBltProc)GetToolTrapAddress(_BitBlt);
//*debug_ptr = (unsigned long)oldBitBlt;
SetToolTrapAddress((UniversalProcPtr)myBitBlt, _BitBlt);
/* restore the a4 world */
SetA4(oldA4);
// *debug_ptr = 0xBEEFDEAD;
SetA4(oldA4);
// *debug_ptr = 0xBEEFDEAD;
}

3896
nubus-to-ztex-gateware/VexRiscv_FbAccel.v
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316
nubus-to-ztex-gateware/blit.c
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@ -22,9 +22,10 @@
#define BASE_RAM 0xF0902000 // FIXME : should be generated : 4-64 KiB of Wishbone SRAM ? ; also in _start
#define BASE_RAM_SIZE 0x00001000 // FIXME : should be generated : 4-64 KiB of Wishbone SRAM ? ; also in _start
#define BASE_BT_REGS 0xF0900000
#define BASE_ACCEL_REGS 0xF0901000
#define mul_HRES(a) ((a) * HRES)
#define mul_sHRES(a) ((a) * sHRES)
//typedef void (*boot_t)(void);
//typedef void (*start_t)(unsigned short, unsigned short, unsigned short, unsigned short, unsigned short, unsigned short, unsigned short, unsigned short);
@ -49,6 +50,26 @@ struct control_blitter {
#define FUN_TEST (1<<FUN_TEST_BIT)
#define FUN_DONE (1<<FUN_DONE_BIT)
struct goblin_bt_regs {
u_int32_t mode;
u_int32_t vbl_mask;
u_int32_t videoctrl;
u_int32_t intr_clear;
u_int32_t reset;
u_int32_t lut_addr;
u_int32_t lut;
u_int32_t debug;
};
enum goblin_bt_mode {
mode_1bit = 0x00,
mode_2bit = 0x01,
mode_4bit = 0x02,
mode_8bit = 0x03,
mode_32bit = 0x10,
mode_16bit = 0x11
};
struct goblin_accel_regs {
u_int32_t reg_status; // 0
u_int32_t reg_cmd;
@ -77,45 +98,51 @@ static inline void flush_cache(void) {
typedef unsigned int unsigned_param_type;
static void rectfill(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color
);
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned_param_type sHRES
);
static void rectfill_pm(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned char pm
);
static void xorrectfill(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color
);
static void xorrectfill_pm(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned char pm
const unsigned char pm,
const unsigned_param_type sHRES
);
static void xorrectfill(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned_param_type sHRES
);
static void xorrectfill_pm(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned char pm,
const unsigned_param_type sHRES
);
static void invert(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re
);
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type sHRES
);
static void bitblit(const unsigned_param_type xs,
const unsigned_param_type ys,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned char pm,
const unsigned char gxop
);
const unsigned_param_type ys,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned char pm,
const unsigned char gxop,
const unsigned_param_type sHRES
);
static void print_hexword(unsigned int v, unsigned int bx, unsigned int by);
static void show_status_on_screen(void);
@ -160,20 +187,32 @@ asm(".global _start\n"
/* also need to figure out the non-coherent caches ... */
void from_reset(void) {
struct goblin_accel_regs* fbc = (struct goblin_accel_regs*)BASE_ACCEL_REGS;
struct goblin_bt_regs* fbt = (struct goblin_bt_regs*)BASE_BT_REGS;
unsigned int cmd = fbc->reg_r5_cmd;
unsigned_param_type sHRES;
switch ((fbt->mode>>24) & 0xFF) { // mode is 8 bits wrong-endian (all fbt is wrong-endian)
case mode_32bit:
sHRES = HRES * 4;
break;
case mode_16bit:
sHRES = HRES * 2;
break;
default:
sHRES = HRES;
break;
}
// fixme; switching to & 0xFFFF will use zext.h, which isn't included in our Vex ATM
switch (cmd & 0xF) {
case FUN_BLIT: {
bitblit(fbc->reg_bitblt_src_x, fbc->reg_bitblt_src_y,
fbc->reg_width, fbc->reg_height,
fbc->reg_bitblt_dst_x, fbc->reg_bitblt_dst_y,
0xFF, 0x3); // GXcopy
0xFF, 0x3, sHRES); // GXcopy
} break;
case FUN_FILL: {
rectfill(fbc->reg_bitblt_dst_x, fbc->reg_bitblt_dst_y,
fbc->reg_width, fbc->reg_height,
fbc->reg_fgcolor);
fbc->reg_fgcolor, sHRES);
} break;
#if 1
case FUN_TEST: {
@ -207,12 +246,13 @@ void from_reset(void) {
#define bitblit_proto_int(a, b, suf) \
static void bitblit##a##b##suf(const unsigned_param_type xs, \
const unsigned_param_type ys, \
const unsigned_param_type wi, \
const unsigned_param_type re, \
const unsigned_param_type xd, \
const unsigned_param_type yd, \
const unsigned char pm \
const unsigned_param_type ys, \
const unsigned_param_type wi, \
const unsigned_param_type re, \
const unsigned_param_type xd, \
const unsigned_param_type yd, \
const unsigned char pm, \
const unsigned_param_type sHRES \
)
#define bitblit_proto(suf) \
bitblit_proto_int(_fwd, _fwd, suf); \
@ -226,18 +266,19 @@ bitblit_proto(_copy_pm);
bitblit_proto(_xor_pm);
#define ROUTE_BITBLIT_PM(pm, bb) \
if (pm == 0xFF) bb(xs, ys, wi, re, xd, yd, pm); \
else bb##_pm(xs, ys, wi, re, xd, yd, pm)
#define ROUTE_BITBLIT_PM(pm, bb) \
if (pm == 0xFF) bb(xs, ys, wi, re, xd, yd, pm, sHRES); \
else bb##_pm(xs, ys, wi, re, xd, yd, pm, sHRES)
static void bitblit(const unsigned_param_type xs,
const unsigned_param_type ys,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned char pm,
const unsigned char gxop
const unsigned_param_type ys,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned char pm,
const unsigned char gxop,
const unsigned_param_type sHRES
) {
struct goblin_accel_regs* fbc = (struct goblin_accel_regs*)BASE_ACCEL_REGS;
@ -284,7 +325,7 @@ static void bitblit(const unsigned_param_type xs,
/* don't bother */
break;
case 0x6: // GXxor
rectfill_pm(xd, yd, wi, re, 0, pm);
rectfill_pm(xd, yd, wi, re, 0, pm, sHRES);
break;
}
}
@ -293,14 +334,15 @@ static void bitblit(const unsigned_param_type xs,
static void rectfill(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned_param_type sHRES
) {
struct goblin_accel_regs* fbc = (struct goblin_accel_regs*)BASE_ACCEL_REGS;
unsigned int i, j;
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd);
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_sHRES(yd) + xd);
unsigned char *dptr_line = dptr;
unsigned char u8color = color & 0xFF;
@ -322,20 +364,21 @@ static void rectfill(const unsigned_param_type xd,
*dptr_elt = u8color;
dptr_elt ++;
}
dptr_line += HRES;
dptr_line += sHRES;
}
}
static void rectfill_pm(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned char pm
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned char pm,
const unsigned_param_type sHRES
) {
struct goblin_accel_regs* fbc = (struct goblin_accel_regs*)BASE_ACCEL_REGS;
unsigned int i, j;
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd);
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_sHRES(yd) + xd);
unsigned char *dptr_line = dptr;
unsigned char u8color = color;
@ -358,20 +401,21 @@ static void rectfill_pm(const unsigned_param_type xd,
*dptr_elt = (u8color & pm) | (*dptr_elt & ~pm);
dptr_elt ++;
}
dptr_line += HRES;
dptr_line += sHRES;
}
}
static void xorrectfill(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned_param_type sHRES
) {
struct goblin_accel_regs* fbc = (struct goblin_accel_regs*)BASE_ACCEL_REGS;
unsigned int i, j;
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd);
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_sHRES(yd) + xd);
unsigned char *dptr_line = dptr;
unsigned char u8color = color & 0xFF;
@ -393,19 +437,20 @@ static void xorrectfill(const unsigned_param_type xd,
*dptr_elt ^= u8color;
dptr_elt ++;
}
dptr_line += HRES;
dptr_line += sHRES;
}
}
static void xorrectfill_pm(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned char pm
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type color,
const unsigned char pm,
const unsigned_param_type sHRES
) {
struct goblin_accel_regs* fbc = (struct goblin_accel_regs*)BASE_ACCEL_REGS;
unsigned int i, j;
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd);
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_sHRES(yd) + xd);
unsigned char *dptr_line = dptr;
unsigned char u8color = color;
@ -428,18 +473,19 @@ static void xorrectfill_pm(const unsigned_param_type xd,
*dptr_elt ^= (u8color & pm);
dptr_elt ++;
}
dptr_line += HRES;
dptr_line += sHRES;
}
}
static void invert(const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re
) {
const unsigned_param_type yd,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type sHRES
) {
struct goblin_accel_regs* fbc = (struct goblin_accel_regs*)BASE_ACCEL_REGS;
unsigned int i, j;
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd);
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_sHRES(yd) + xd);
unsigned char *dptr_line = dptr;
for (j = 0 ; j < re ; j++) {
@ -459,7 +505,7 @@ static void invert(const unsigned_param_type xd,
*dptr_elt = ~(*dptr_elt);
dptr_elt ++;
}
dptr_line += HRES;
dptr_line += sHRES;
}
}
@ -479,10 +525,11 @@ static void invert(const unsigned_param_type xd,
const unsigned_param_type re, \
const unsigned_param_type xd, \
const unsigned_param_type yd, \
const unsigned char pm) { \
const unsigned char pm, \
const unsigned_param_type sHRES) { \
unsigned int i, j; \
unsigned char *sptr = (((unsigned char *)BASE_FB) + mul_HRES(ys) + xs); \
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd); \
unsigned char *sptr = (((unsigned char *)BASE_FB) + mul_sHRES(ys) + xs); \
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_sHRES(yd) + xd); \
unsigned char *sptr_line = sptr; \
unsigned char *dptr_line = dptr; \
/*const unsigned char npm = ~pm;*/ \
@ -537,8 +584,8 @@ static void invert(const unsigned_param_type xd,
dptr_elt ++; \
sptr_elt ++; \
} \
sptr_line += HRES; \
dptr_line += HRES; \
sptr_line += sHRES; \
dptr_line += sHRES; \
} \
}
@ -549,10 +596,11 @@ static void invert(const unsigned_param_type xd,
const unsigned_param_type re, \
const unsigned_param_type xd, \
const unsigned_param_type yd, \
const unsigned char pm) { \
const unsigned char pm, \
const unsigned_param_type sHRES) { \
unsigned int i, j; \
unsigned char *sptr = (((unsigned char *)BASE_FB) + mul_HRES(ys) + xs); \
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd); \
unsigned char *sptr = (((unsigned char *)BASE_FB) + mul_sHRES(ys) + xs); \
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_sHRES(yd) + xd); \
unsigned char *sptr_line = sptr + wi - 1; \
unsigned char *dptr_line = dptr + wi - 1; \
const unsigned char npm = ~pm; \
@ -565,8 +613,8 @@ static void invert(const unsigned_param_type xd,
dptr_elt --; \
sptr_elt --; \
} \
sptr_line += HRES; \
dptr_line += HRES; \
sptr_line += sHRES; \
dptr_line += sHRES; \
} \
}
@ -577,12 +625,13 @@ static void invert(const unsigned_param_type xd,
const unsigned_param_type re, \
const unsigned_param_type xd, \
const unsigned_param_type yd, \
const unsigned char pm) { \
const unsigned char pm, \
const unsigned_param_type sHRES) { \
unsigned int i, j; \
unsigned char *sptr = (((unsigned char *)BASE_FB) + mul_HRES(ys) + xs); \
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd); \
unsigned char *sptr_line = sptr + mul_HRES(re-1); \
unsigned char *dptr_line = dptr + mul_HRES(re-1); \
unsigned char *sptr = (((unsigned char *)BASE_FB) + mul_sHRES(ys) + xs); \
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_sHRES(yd) + xd); \
unsigned char *sptr_line = sptr + mul_sHRES(re-1); \
unsigned char *dptr_line = dptr + mul_sHRES(re-1); \
const unsigned char npm = ~pm; \
\
for (j = 0 ; j < re ; j++) { \
@ -639,8 +688,8 @@ static void invert(const unsigned_param_type xd,
dptr_elt ++; \
sptr_elt ++; \
} \
sptr_line -= HRES; \
dptr_line -= HRES; \
sptr_line -= sHRES; \
dptr_line -= sHRES; \
} \
}
@ -655,69 +704,4 @@ BLIT_ALLDIR(copy, COPY)
BLIT_ALLDIR(xor, XOR)
BLIT_ALLDIR(copy_pm, COPY_PM)
BLIT_ALLDIR(xor_pm, XOR_PM)
#if 0
else if ((xd & 0xf) == 0) {
unsigned int fsr_cst = xs & 0x3;
unsigned char* sptr_elt_al = sptr_elt - fsr_cst;
unsigned int src0 = ((unsigned int*)sptr_elt_al)[0];
for ( ; i < (wi&(~0xf)) ; i+= 16) {
unsigned int src1, val;
src1 = ((unsigned int*)sptr_elt_al)[1];
val = _rv32_fsr(src0, src1, fsr_cst);
((unsigned int*)dptr_elt)[0] = val;
src0 = src1;
src1 = ((unsigned int*)sptr_elt_al)[2];
val = _rv32_fsr(src0, src1, fsr_cst);
((unsigned int*)dptr_elt)[1] = val;
src0 = src1;
src1 = ((unsigned int*)sptr_elt_al)[3];
val = _rv32_fsr(src0, src1, fsr_cst);
((unsigned int*)dptr_elt)[2] = val;
src0 = src1;
src1 = ((unsigned int*)sptr_elt_al)[4];
val = _rv32_fsr(src0, src1, fsr_cst);
((unsigned int*)dptr_elt)[3] = val;
src0 = src1;
dptr_elt += 16;
sptr_elt_al += 16;
}
}
#endif
#if 0
static void bitblit_bwd_bwd_copy(const unsigned_param_type xs,
const unsigned_param_type ys,
const unsigned_param_type wi,
const unsigned_param_type re,
const unsigned_param_type xd,
const unsigned_param_type yd,
const unsigned char pm
) {
unsigned int i, j;
unsigned char *sptr = (((unsigned char *)BASE_FB) + mul_HRES(ys) + xs);
unsigned char *dptr = (((unsigned char *)BASE_FB) + mul_HRES(yd) + xd);
unsigned char *sptr_line = sptr + mul_HRES(re-1);
unsigned char *dptr_line = dptr + mul_HRES(re-1);
// flush_cache(); // handled in boot()
for (j = 0 ; j < re ; j++) {
unsigned char *sptr_elt = sptr_line + wi - 1;
unsigned char *dptr_elt = dptr_line + wi - 1;
for (i = 0 ; i < wi ; i++) {
*dptr_elt = *sptr_elt;
dptr_elt --;
sptr_elt --;
}
sptr_line -= HRES;
dptr_line -= HRES;
}
}
#endif

2
nubus-to-ztex-gateware/blit.sh
View File

@ -18,7 +18,7 @@ GCC=${GCCDIR}/bin/${GCCPFX}gcc
OBJCOPY=${GCCDIR}/bin/${GCCPFX}objcopy
OPT=-Os #-fno-inline
ARCH=rv32i_zba_zbb_zbt
ARCH=rv32im_zba_zbb_zbt
PARAM="-DHRES=${HRES} -DVRES=${VRES} -DBASE_FB=${BASE_FB}"

2
nubus-to-ztex-gateware/goblin_accel.py
View File

@ -12,7 +12,7 @@ class GoblinAccel(Module): # AutoCSR ?
# reg access
self.bus = bus = wishbone.Interface()
self.COORD_BITS = COORD_BITS = 12 #
self.COORD_BITS = COORD_BITS = 16 # need enough bytes for 32-bits wat widest resolution
reg_status = Signal(32) # 0
reg_cmd = Signal(32) # 1

17
nubus-to-ztex-gateware/nubus_full.py
View File

@ -94,7 +94,7 @@ class NuBus(Module):
("data", 32),
("sel", 4),
]
self.submodules.write_fifo = write_fifo = ClockDomainsRenamer({"read": "sys", "write": "nubus"})(AsyncFIFOBuffered(width=layout_len(write_fifo_layout), depth=8))
self.submodules.write_fifo = write_fifo = ClockDomainsRenamer({"read": "sys", "write": "nubus"})(AsyncFIFOBuffered(width=layout_len(write_fifo_layout), depth=16))
write_fifo_dout = Record(write_fifo_layout)
self.comb += write_fifo_dout.raw_bits().eq(write_fifo.dout)
write_fifo_din = Record(write_fifo_layout)
@ -201,12 +201,17 @@ class NuBus(Module):
# )
#)
slave_fsm.act("NubusWriteDataToFIFO",
write_fifo.we.eq(1),
tmo_oe.eq(1),
tm0_o_n.eq(0),
tm1_o_n.eq(0),
ack_o_n.eq(0),
NextState("Idle"),
tm0_o_n.eq(1),
tm1_o_n.eq(1),
ack_o_n.eq(1),
If(write_fifo.writable,
write_fifo.we.eq(1),
tm0_o_n.eq(0),
tm1_o_n.eq(0),
ack_o_n.eq(0),
NextState("Idle"),
)
)
# connect the write FIFO inputs