Rounding FMA
This commit is contained in:
Romain Dolbeau
parent
759cfdbf4f
commit
87d04b187f
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@ -0,0 +1,596 @@
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// WARNING: this is auto-generated code!
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// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
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package vexriscv.plugin
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import spinal.core._
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import vexriscv.{Stageable, DecoderService, VexRiscv}
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object GoblinPlugin {
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object GoblinCtrlpdpikadd8Enum extends SpinalEnum(binarySequential) {
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val CTRL_UKADD8, CTRL_UKSUB8 = newElement()
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}
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object GoblinCtrlEnum extends SpinalEnum(binarySequential) {
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val CTRL_pdpikadd8 = newElement()
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}
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object GoblinCtrlpdpikadd8 extends Stageable(GoblinCtrlpdpikadd8Enum())
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object GoblinCtrl extends Stageable(GoblinCtrlEnum())
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// Prologue
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def fun_add8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = (rs1( 7 downto 0).asUInt + rs2( 7 downto 0).asUInt).asBits.resize(8)
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val b1 = (rs1(15 downto 8).asUInt + rs2(15 downto 8).asUInt).asBits.resize(8)
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val b2 = (rs1(23 downto 16).asUInt + rs2(23 downto 16).asUInt).asBits.resize(8)
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val b3 = (rs1(31 downto 24).asUInt + rs2(31 downto 24).asUInt).asBits.resize(8)
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_radd8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = ((rs1( 7) ## rs1( 7 downto 0)).asSInt + (rs2( 7) ## rs2( 7 downto 0)).asSInt).asBits.resize(9)
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val b1 = ((rs1(15) ## rs1(15 downto 8)).asSInt + (rs2(15) ## rs2(15 downto 8)).asSInt).asBits.resize(9)
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val b2 = ((rs1(23) ## rs1(23 downto 16)).asSInt + (rs2(23) ## rs2(23 downto 16)).asSInt).asBits.resize(9)
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val b3 = ((rs1(31) ## rs1(31 downto 24)).asSInt + (rs2(31) ## rs2(31 downto 24)).asSInt).asBits.resize(9)
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b3(8 downto 1) ## b2(8 downto 1) ## b1(8 downto 1) ## b0(8 downto 1) // return value
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}
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def fun_rsub8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = ((rs1( 7) ## rs1( 7 downto 0)).asSInt - (rs2( 7) ## rs2( 7 downto 0)).asSInt).asBits.resize(9)
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val b1 = ((rs1(15) ## rs1(15 downto 8)).asSInt - (rs2(15) ## rs2(15 downto 8)).asSInt).asBits.resize(9)
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val b2 = ((rs1(23) ## rs1(23 downto 16)).asSInt - (rs2(23) ## rs2(23 downto 16)).asSInt).asBits.resize(9)
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val b3 = ((rs1(31) ## rs1(31 downto 24)).asSInt - (rs2(31) ## rs2(31 downto 24)).asSInt).asBits.resize(9)
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b3(8 downto 1) ## b2(8 downto 1) ## b1(8 downto 1) ## b0(8 downto 1) // return value
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}
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def fun_add16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = (rs1(15 downto 0).asUInt + rs2(15 downto 0).asUInt).asBits.resize(16)
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val h1 = (rs1(31 downto 16).asUInt + rs2(31 downto 16).asUInt).asBits.resize(16)
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h1 ## h0 // return value
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}
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def fun_radd16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = ((rs1(15) ## rs1(15 downto 0)).asSInt + (rs2(15) ## rs2(15 downto 0)).asSInt).asBits.resize(17)
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val h1 = ((rs1(31) ## rs1(31 downto 16)).asSInt + (rs2(31) ## rs2(31 downto 16)).asSInt).asBits.resize(17)
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h1(16 downto 1) ## h0(16 downto 1) // return value
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}
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def fun_rsub16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = ((rs1(15) ## rs1(15 downto 0)).asSInt - (rs2(15) ## rs2(15 downto 0)).asSInt).asBits.resize(17)
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val h1 = ((rs1(31) ## rs1(31 downto 16)).asSInt - (rs2(31) ## rs2(31 downto 16)).asSInt).asBits.resize(17)
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h1(16 downto 1) ## h0(16 downto 1) // return value
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}
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def fun_radd32(rs1: Bits, rs2: Bits) : Bits = {
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val s = ((rs1(31) ## rs1).asSInt + (rs2(31) ## rs2).asSInt).asBits.resize(33)
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s(32 downto 1) // return value
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}
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def fun_rsub32(rs1: Bits, rs2: Bits) : Bits = {
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val s = ((rs1(31) ## rs1).asSInt - (rs2(31) ## rs2).asSInt).asBits.resize(33)
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s(32 downto 1) // return value
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}
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def fun_ave(rs1: Bits, rs2: Bits) : Bits = {
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val inter = (1 + (rs1 ## B"1'b0").asUInt + (rs2 ## B"1'b0").asUInt).asBits.resize(33)
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inter(32 downto 1) // return value
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}
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def fun_bitrev(rs1: Bits, rs2: Bits) : Bits = {
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val msb = rs2(4 downto 0).asUInt
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val rs1r = rs1(0) ## rs1(1) ## rs1(2) ## rs1(3) ## rs1(4) ## rs1(5) ## rs1(6) ## rs1(7) ## rs1(8) ## rs1(9) ## rs1(10) ## rs1(11) ## rs1(12) ## rs1(13) ## rs1(14) ## rs1(15) ## rs1(16) ## rs1(17) ## rs1(18) ## rs1(19) ## rs1(20) ## rs1(21) ## rs1(22) ## rs1(23) ## rs1(24) ## rs1(25) ## rs1(26) ## rs1(27) ## rs1(28) ## rs1(29) ## rs1(30) ## rs1(31)
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val rs1rs = rs1r |>> (31-msb)
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rs1rs // return value
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}
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// this is trying to look like DOI 10.2478/jee-2015-0054
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def fun_clz_NLCi(x:Bits): Bits = {
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val r2 = (~(x(0) | x(1) | x(2) | x(3)))
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val r1 = (~(x(2) | x(3)))
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val r0 = (~(x(3) | (x(1) & ~x(2))))
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val r = r2 ## r1 ## r0
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r // return value
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}
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def fun_clz_byte(in: Bits): Bits = {
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val nlc1 = fun_clz_NLCi(in( 7 downto 4))
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val nlc0 = fun_clz_NLCi(in( 3 downto 0))
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val x = ((nlc1(2).asUInt === 1) ? (4 + nlc0(1 downto 0).asUInt) | (nlc1(1 downto 0).asUInt))
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val y = B"8'x08"
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((nlc0(2).asUInt === 1) && (nlc1(2).asUInt === 1)) ? y | x.asBits.resize(8) // return value
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}
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def fun_clrs8(rs1: Bits) : Bits = {
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val b0 = rs1( 7 downto 0)
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val b1 = rs1(15 downto 8)
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val b2 = rs1(23 downto 16)
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val b3 = rs1(31 downto 24)
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val b0s = (b0(7).asUInt === 1) ? (~b0) | (b0)
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val b1s = (b1(7).asUInt === 1) ? (~b1) | (b1)
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val b2s = (b2(7).asUInt === 1) ? (~b2) | (b2)
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val b3s = (b3(7).asUInt === 1) ? (~b3) | (b3)
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val c0 = fun_clz_byte(b0s).asUInt - 1
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val c1 = fun_clz_byte(b1s).asUInt - 1
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val c2 = fun_clz_byte(b2s).asUInt - 1
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val c3 = fun_clz_byte(b3s).asUInt - 1
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c3.asBits.resize(8) ## c2.asBits.resize(8) ## c1.asBits.resize(8) ## c0.asBits.resize(8) // return value
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}
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def fun_clo8(rs1: Bits) : Bits = {
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val b0 = rs1( 7 downto 0)
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val b1 = rs1(15 downto 8)
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val b2 = rs1(23 downto 16)
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val b3 = rs1(31 downto 24)
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val c0 = fun_clz_byte(~b0)
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val c1 = fun_clz_byte(~b1)
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val c2 = fun_clz_byte(~b2)
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val c3 = fun_clz_byte(~b3)
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c3 ## c2 ## c1 ## c0 // return value
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}
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def fun_clz8(rs1: Bits) : Bits = {
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val b0 = rs1( 7 downto 0)
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val b1 = rs1(15 downto 8)
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val b2 = rs1(23 downto 16)
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val b3 = rs1(31 downto 24)
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val c0 = fun_clz_byte(b0)
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val c1 = fun_clz_byte(b1)
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val c2 = fun_clz_byte(b2)
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val c3 = fun_clz_byte(b3)
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c3 ## c2 ## c1 ## c0 // return value
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}
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def fun_swap8(rs1: Bits) : Bits = {
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val b0 = rs1( 7 downto 0)
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val b1 = rs1(15 downto 8)
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val b2 = rs1(23 downto 16)
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val b3 = rs1(31 downto 24)
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b2 ## b3 ## b0 ## b1 // return value
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}
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def fun_swap16(rs1: Bits) : Bits = {
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val h0 = rs1(15 downto 0)
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val h1 = rs1(31 downto 16)
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h0 ## h1 // return value
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}
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def fun_cmpeq8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = (rs1( 7 downto 0).asUInt === rs2( 7 downto 0).asUInt) ? B"8'xFF" | B"8'x00"
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val b1 = (rs1(15 downto 8).asUInt === rs2(15 downto 8).asUInt) ? B"8'xFF" | B"8'x00"
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val b2 = (rs1(23 downto 16).asUInt === rs2(23 downto 16).asUInt) ? B"8'xFF" | B"8'x00"
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val b3 = (rs1(31 downto 24).asUInt === rs2(31 downto 24).asUInt) ? B"8'xFF" | B"8'x00"
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_cmpeq16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = (rs1(15 downto 0).asUInt === rs2(15 downto 0).asUInt) ? B"16'xFFFF" | B"16'x0000"
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val h1 = (rs1(31 downto 16).asUInt === rs2(31 downto 16).asUInt) ? B"16'xFFFF" | B"16'x0000"
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h1 ## h0 // return value
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}
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def fun_pkbbtt16(rs1: Bits, rs2: Bits, h:UInt, l:UInt) : Bits = {
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val hr = (h === 0) ? rs1(15 downto 0) | rs1(31 downto 16)
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val hl = (l === 0) ? rs2(15 downto 0) | rs2(31 downto 16)
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hr ## hl // return value
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}
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def fun_scmple8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = (rs1( 7 downto 0).asSInt <= rs2( 7 downto 0).asSInt) ? B"8'xFF" | B"8'x00"
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val b1 = (rs1(15 downto 8).asSInt <= rs2(15 downto 8).asSInt) ? B"8'xFF" | B"8'x00"
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val b2 = (rs1(23 downto 16).asSInt <= rs2(23 downto 16).asSInt) ? B"8'xFF" | B"8'x00"
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val b3 = (rs1(31 downto 24).asSInt <= rs2(31 downto 24).asSInt) ? B"8'xFF" | B"8'x00"
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_scmple16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = (rs1(15 downto 0).asSInt <= rs2(15 downto 0).asSInt) ? B"16'xFFFF" | B"16'x0000"
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val h1 = (rs1(31 downto 16).asSInt <= rs2(31 downto 16).asSInt) ? B"16'xFFFF" | B"16'x0000"
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h1 ## h0 // return value
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}
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def fun_scmplt8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = (rs1( 7 downto 0).asSInt < rs2( 7 downto 0).asSInt) ? B"8'xFF" | B"8'x00"
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val b1 = (rs1(15 downto 8).asSInt < rs2(15 downto 8).asSInt) ? B"8'xFF" | B"8'x00"
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val b2 = (rs1(23 downto 16).asSInt < rs2(23 downto 16).asSInt) ? B"8'xFF" | B"8'x00"
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val b3 = (rs1(31 downto 24).asSInt < rs2(31 downto 24).asSInt) ? B"8'xFF" | B"8'x00"
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_scmplt16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = (rs1(15 downto 0).asSInt < rs2(15 downto 0).asSInt) ? B"16'xFFFF" | B"16'x0000"
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val h1 = (rs1(31 downto 16).asSInt < rs2(31 downto 16).asSInt) ? B"16'xFFFF" | B"16'x0000"
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h1 ## h0 // return value
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}
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def fun_ucmple8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = (rs1( 7 downto 0).asUInt <= rs2( 7 downto 0).asUInt) ? B"8'xFF" | B"8'x00"
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val b1 = (rs1(15 downto 8).asUInt <= rs2(15 downto 8).asUInt) ? B"8'xFF" | B"8'x00"
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val b2 = (rs1(23 downto 16).asUInt <= rs2(23 downto 16).asUInt) ? B"8'xFF" | B"8'x00"
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val b3 = (rs1(31 downto 24).asUInt <= rs2(31 downto 24).asUInt) ? B"8'xFF" | B"8'x00"
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_ucmple16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = (rs1(15 downto 0).asUInt <= rs2(15 downto 0).asUInt) ? B"16'xFFFF" | B"16'x0000"
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val h1 = (rs1(31 downto 16).asUInt <= rs2(31 downto 16).asUInt) ? B"16'xFFFF" | B"16'x0000"
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h1 ## h0 // return value
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}
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def fun_ucmplt8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = (rs1( 7 downto 0).asUInt < rs2( 7 downto 0).asUInt) ? B"8'xFF" | B"8'x00"
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val b1 = (rs1(15 downto 8).asUInt < rs2(15 downto 8).asUInt) ? B"8'xFF" | B"8'x00"
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val b2 = (rs1(23 downto 16).asUInt < rs2(23 downto 16).asUInt) ? B"8'xFF" | B"8'x00"
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val b3 = (rs1(31 downto 24).asUInt < rs2(31 downto 24).asUInt) ? B"8'xFF" | B"8'x00"
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_ucmplt16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = (rs1(15 downto 0).asUInt < rs2(15 downto 0).asUInt) ? B"16'xFFFF" | B"16'x0000"
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val h1 = (rs1(31 downto 16).asUInt < rs2(31 downto 16).asUInt) ? B"16'xFFFF" | B"16'x0000"
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h1 ## h0 // return value
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}
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def fun_sll8(rs1: Bits, rs2: Bits) : Bits = {
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val o = rs2(2 downto 0).asUInt
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val b0 = rs1( 7 downto 0).asUInt |<< o
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val b1 = rs1(15 downto 8).asUInt |<< o
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val b2 = rs1(23 downto 16).asUInt |<< o
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val b3 = rs1(31 downto 24).asUInt |<< o
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_srl8(rs1: Bits, rs2: Bits) : Bits = {
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val o = rs2(2 downto 0).asUInt
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val b0 = rs1( 7 downto 0).asUInt |>> o
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val b1 = rs1(15 downto 8).asUInt |>> o
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val b2 = rs1(23 downto 16).asUInt |>> o
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val b3 = rs1(31 downto 24).asUInt |>> o
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_sra8(rs1: Bits, rs2: Bits) : Bits = {
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val o = rs2(2 downto 0).asUInt
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val b0 = rs1( 7 downto 0).asSInt |>> o
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val b1 = rs1(15 downto 8).asSInt |>> o
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val b2 = rs1(23 downto 16).asSInt |>> o
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val b3 = rs1(31 downto 24).asSInt |>> o
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_sll16(rs1: Bits, rs2: Bits) : Bits = {
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val o = rs2(3 downto 0).asUInt
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val h0 = rs1(15 downto 0).asUInt |<< o
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val h1 = rs1(31 downto 16).asUInt |<< o
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h1 ## h0 // return value
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}
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def fun_srl16(rs1: Bits, rs2: Bits) : Bits = {
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val o = rs2(3 downto 0).asUInt
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val h0 = rs1(15 downto 0).asUInt |>> o
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val h1 = rs1(31 downto 16).asUInt |>> o
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h1 ## h0 // return value
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}
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def fun_sra16(rs1: Bits, rs2: Bits) : Bits = {
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val o = rs2(3 downto 0).asUInt
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val h0 = rs1(15 downto 0).asSInt |>> o
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val h1 = rs1(31 downto 16).asSInt |>> o
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h1 ## h0 // return value
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}
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def fun_smax8(rs1: Bits, rs2: Bits) : Bits = {
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val b0 = (rs1( 7 downto 0).asSInt >= rs2( 7 downto 0).asSInt) ? rs1( 7 downto 0) | rs2( 7 downto 0)
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val b1 = (rs1(15 downto 8).asSInt >= rs2(15 downto 8).asSInt) ? rs1(15 downto 8) | rs2(15 downto 8)
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val b2 = (rs1(23 downto 16).asSInt >= rs2(23 downto 16).asSInt) ? rs1(23 downto 16) | rs2(23 downto 16)
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val b3 = (rs1(31 downto 24).asSInt >= rs2(31 downto 24).asSInt) ? rs1(31 downto 24) | rs2(31 downto 24)
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b3 ## b2 ## b1 ## b0 // return value
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}
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def fun_smax16(rs1: Bits, rs2: Bits) : Bits = {
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val h0 = (rs1(15 downto 0).asSInt >= rs2(15 downto 0).asSInt) ? rs1(15 downto 0) | rs2(15 downto 0)
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val h1 = (rs1(31 downto 16).asSInt >= rs2(31 downto 16).asSInt) ? rs1(31 downto 16) | rs2(31 downto 16)
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h1 ## h0 // return value
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}
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def fun_smin8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = (rs1( 7 downto 0).asSInt <= rs2( 7 downto 0).asSInt) ? rs1( 7 downto 0) | rs2( 7 downto 0)
|
||||
val b1 = (rs1(15 downto 8).asSInt <= rs2(15 downto 8).asSInt) ? rs1(15 downto 8) | rs2(15 downto 8)
|
||||
val b2 = (rs1(23 downto 16).asSInt <= rs2(23 downto 16).asSInt) ? rs1(23 downto 16) | rs2(23 downto 16)
|
||||
val b3 = (rs1(31 downto 24).asSInt <= rs2(31 downto 24).asSInt) ? rs1(31 downto 24) | rs2(31 downto 24)
|
||||
|
||||
b3 ## b2 ## b1 ## b0 // return value
|
||||
}
|
||||
def fun_smin16(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val h0 = (rs1(15 downto 0).asSInt <= rs2(15 downto 0).asSInt) ? rs1(15 downto 0) | rs2(15 downto 0)
|
||||
val h1 = (rs1(31 downto 16).asSInt <= rs2(31 downto 16).asSInt) ? rs1(31 downto 16) | rs2(31 downto 16)
|
||||
|
||||
h1 ## h0 // return value
|
||||
}
|
||||
def fun_umax8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = (rs1( 7 downto 0).asUInt >= rs2( 7 downto 0).asUInt) ? rs1( 7 downto 0) | rs2( 7 downto 0)
|
||||
val b1 = (rs1(15 downto 8).asUInt >= rs2(15 downto 8).asUInt) ? rs1(15 downto 8) | rs2(15 downto 8)
|
||||
val b2 = (rs1(23 downto 16).asUInt >= rs2(23 downto 16).asUInt) ? rs1(23 downto 16) | rs2(23 downto 16)
|
||||
val b3 = (rs1(31 downto 24).asUInt >= rs2(31 downto 24).asUInt) ? rs1(31 downto 24) | rs2(31 downto 24)
|
||||
|
||||
b3 ## b2 ## b1 ## b0 // return value
|
||||
}
|
||||
def fun_umax16(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val h0 = (rs1(15 downto 0).asUInt >= rs2(15 downto 0).asUInt) ? rs1(15 downto 0) | rs2(15 downto 0)
|
||||
val h1 = (rs1(31 downto 16).asUInt >= rs2(31 downto 16).asUInt) ? rs1(31 downto 16) | rs2(31 downto 16)
|
||||
|
||||
h1 ## h0 // return value
|
||||
}
|
||||
def fun_umin8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = (rs1( 7 downto 0).asUInt <= rs2( 7 downto 0).asUInt) ? rs1( 7 downto 0) | rs2( 7 downto 0)
|
||||
val b1 = (rs1(15 downto 8).asUInt <= rs2(15 downto 8).asUInt) ? rs1(15 downto 8) | rs2(15 downto 8)
|
||||
val b2 = (rs1(23 downto 16).asUInt <= rs2(23 downto 16).asUInt) ? rs1(23 downto 16) | rs2(23 downto 16)
|
||||
val b3 = (rs1(31 downto 24).asUInt <= rs2(31 downto 24).asUInt) ? rs1(31 downto 24) | rs2(31 downto 24)
|
||||
|
||||
b3 ## b2 ## b1 ## b0 // return value
|
||||
}
|
||||
def fun_umin16(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val h0 = (rs1(15 downto 0).asUInt <= rs2(15 downto 0).asUInt) ? rs1(15 downto 0) | rs2(15 downto 0)
|
||||
val h1 = (rs1(31 downto 16).asUInt <= rs2(31 downto 16).asUInt) ? rs1(31 downto 16) | rs2(31 downto 16)
|
||||
|
||||
h1 ## h0 // return value
|
||||
}
|
||||
|
||||
def fun_sub8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = (rs1( 7 downto 0).asUInt - rs2( 7 downto 0).asUInt).asBits.resize(8)
|
||||
val b1 = (rs1(15 downto 8).asUInt - rs2(15 downto 8).asUInt).asBits.resize(8)
|
||||
val b2 = (rs1(23 downto 16).asUInt - rs2(23 downto 16).asUInt).asBits.resize(8)
|
||||
val b3 = (rs1(31 downto 24).asUInt - rs2(31 downto 24).asUInt).asBits.resize(8)
|
||||
|
||||
b3 ## b2 ## b1 ## b0 // return value
|
||||
}
|
||||
def fun_sub16(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val h0 = (rs1(15 downto 0).asUInt - rs2(15 downto 0).asUInt).asBits.resize(16)
|
||||
val h1 = (rs1(31 downto 16).asUInt - rs2(31 downto 16).asUInt).asBits.resize(16)
|
||||
|
||||
h1 ## h0 // return value
|
||||
}
|
||||
|
||||
def fun_uradd8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = ((B"1'b0" ## rs1( 7 downto 0)).asUInt + (B"1'b0" ## rs2( 7 downto 0)).asUInt).asBits.resize(9)
|
||||
val b1 = ((B"1'b0" ## rs1(15 downto 8)).asUInt + (B"1'b0" ## rs2(15 downto 8)).asUInt).asBits.resize(9)
|
||||
val b2 = ((B"1'b0" ## rs1(23 downto 16)).asUInt + (B"1'b0" ## rs2(23 downto 16)).asUInt).asBits.resize(9)
|
||||
val b3 = ((B"1'b0" ## rs1(31 downto 24)).asUInt + (B"1'b0" ## rs2(31 downto 24)).asUInt).asBits.resize(9)
|
||||
|
||||
b3(8 downto 1) ## b2(8 downto 1) ## b1(8 downto 1) ## b0(8 downto 1) // return value
|
||||
}
|
||||
def fun_ursub8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = ((B"1'b0" ## rs1( 7 downto 0)).asUInt - (B"1'b0" ## rs2( 7 downto 0)).asUInt).asBits.resize(9)
|
||||
val b1 = ((B"1'b0" ## rs1(15 downto 8)).asUInt - (B"1'b0" ## rs2(15 downto 8)).asUInt).asBits.resize(9)
|
||||
val b2 = ((B"1'b0" ## rs1(23 downto 16)).asUInt - (B"1'b0" ## rs2(23 downto 16)).asUInt).asBits.resize(9)
|
||||
val b3 = ((B"1'b0" ## rs1(31 downto 24)).asUInt - (B"1'b0" ## rs2(31 downto 24)).asUInt).asBits.resize(9)
|
||||
|
||||
b3(8 downto 1) ## b2(8 downto 1) ## b1(8 downto 1) ## b0(8 downto 1) // return value
|
||||
}
|
||||
def fun_uradd16(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val h0 = ((B"1'b0" ## rs1(15 downto 0)).asUInt + (B"1'b0" ## rs2(15 downto 0)).asUInt).asBits.resize(17)
|
||||
val h1 = ((B"1'b0" ## rs1(31 downto 16)).asUInt + (B"1'b0" ## rs2(31 downto 16)).asUInt).asBits.resize(17)
|
||||
|
||||
h1(16 downto 1) ## h0(16 downto 1) // return value
|
||||
}
|
||||
def fun_ursub16(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val h0 = ((B"1'b0" ## rs1(15 downto 0)).asUInt - (B"1'b0" ## rs2(15 downto 0)).asUInt).asBits.resize(17)
|
||||
val h1 = ((B"1'b0" ## rs1(31 downto 16)).asUInt - (B"1'b0" ## rs2(31 downto 16)).asUInt).asBits.resize(17)
|
||||
|
||||
h1(16 downto 1) ## h0(16 downto 1) // return value
|
||||
}
|
||||
def fun_uradd32(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val s = ((B"1'b0" ## rs1).asUInt + (B"1'b0" ## rs2).asUInt).asBits.resize(33)
|
||||
|
||||
s(32 downto 1) // return value
|
||||
}
|
||||
def fun_ursub32(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val s = ((B"1'b0" ## rs1).asUInt - (B"1'b0" ## rs2).asUInt).asBits.resize(33)
|
||||
|
||||
s(32 downto 1) // return value
|
||||
}
|
||||
|
||||
def fun_pbsada(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
|
||||
// zero-extend to handle as unsigned
|
||||
val b0 = ((B"1'b0" ## rs1( 7 downto 0)).asSInt - (B"1'b0" ## rs2( 7 downto 0)).asSInt)
|
||||
val b1 = ((B"1'b0" ## rs1(15 downto 8)).asSInt - (B"1'b0" ## rs2(15 downto 8)).asSInt)
|
||||
val b2 = ((B"1'b0" ## rs1(23 downto 16)).asSInt - (B"1'b0" ## rs2(23 downto 16)).asSInt)
|
||||
val b3 = ((B"1'b0" ## rs1(31 downto 24)).asSInt - (B"1'b0" ## rs2(31 downto 24)).asSInt)
|
||||
|
||||
val sum = rs3.asUInt + b0.abs + b1.abs + b2.abs + b3.abs
|
||||
|
||||
sum.asBits.resize(32) // return value
|
||||
}
|
||||
|
||||
def fun_insb(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
|
||||
val idx = rs2(1 downto 0).asUInt
|
||||
val b = rs1(7 downto 0)
|
||||
val r = (idx).mux(
|
||||
0 -> rs3(31 downto 8) ## b,
|
||||
1 -> rs3(31 downto 16) ## b ## rs3( 7 downto 0),
|
||||
2 -> rs3(31 downto 24) ## b ## rs3(15 downto 0),
|
||||
3 -> b ## rs3(23 downto 0)
|
||||
)
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_smaqa(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
|
||||
val h0 = (rs1( 7 downto 0).asSInt * rs2( 7 downto 0).asSInt).resize(18)
|
||||
val h1 = (rs1(15 downto 8).asSInt * rs2(15 downto 8).asSInt).resize(18)
|
||||
val h2 = (rs1(23 downto 16).asSInt * rs2(23 downto 16).asSInt).resize(18)
|
||||
val h3 = (rs1(31 downto 24).asSInt * rs2(31 downto 24).asSInt).resize(18)
|
||||
val r = rs3.asSInt + (h0 + h1 + h2 + h3)
|
||||
|
||||
r.asBits.resize(32) // return value
|
||||
}
|
||||
def fun_umaqa(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
|
||||
// 18 bits needed so that intermediate sums don't overflow
|
||||
val h0 = (rs1( 7 downto 0).asUInt * rs2( 7 downto 0).asUInt).resize(18)
|
||||
val h1 = (rs1(15 downto 8).asUInt * rs2(15 downto 8).asUInt).resize(18)
|
||||
val h2 = (rs1(23 downto 16).asUInt * rs2(23 downto 16).asUInt).resize(18)
|
||||
val h3 = (rs1(31 downto 24).asUInt * rs2(31 downto 24).asUInt).resize(18)
|
||||
val r = rs3.asUInt + (h0 + h1 + h2 + h3)
|
||||
|
||||
r.asBits.resize(32) // return value
|
||||
}
|
||||
|
||||
def fun_zunpkd8(rs1: Bits, ctrl: Bits) : Bits = {
|
||||
val r = (ctrl).mux(
|
||||
default -> rs1(15 downto 8).resize(16) ## rs1( 7 downto 0).resize(16), // B"4'b0100"
|
||||
B"4'b0101" -> rs1(23 downto 16).resize(16) ## rs1( 7 downto 0).resize(16),
|
||||
B"4'b0110" -> rs1(31 downto 24).resize(16) ## rs1( 7 downto 0).resize(16),
|
||||
B"4'b0111" -> rs1(31 downto 24).resize(16) ## rs1(15 downto 8).resize(16),
|
||||
B"4'b1011" -> rs1(31 downto 24).resize(16) ## rs1(23 downto 16).resize(16)
|
||||
)
|
||||
r // return value
|
||||
}
|
||||
def fun_sunpkd8(rs1: Bits, ctrl: Bits) : Bits = {
|
||||
val r = (ctrl).mux(
|
||||
default -> rs1(15 downto 8).asSInt.resize(16).asBits ## rs1( 7 downto 0).asSInt.resize(16).asBits, // B"4'b0100"
|
||||
B"4'b0101" -> rs1(23 downto 16).asSInt.resize(16).asBits ## rs1( 7 downto 0).asSInt.resize(16).asBits,
|
||||
B"4'b0110" -> rs1(31 downto 24).asSInt.resize(16).asBits ## rs1( 7 downto 0).asSInt.resize(16).asBits,
|
||||
B"4'b0111" -> rs1(31 downto 24).asSInt.resize(16).asBits ## rs1(15 downto 8).asSInt.resize(16).asBits,
|
||||
B"4'b1011" -> rs1(31 downto 24).asSInt.resize(16).asBits ## rs1(23 downto 16).asSInt.resize(16).asBits
|
||||
)
|
||||
r // return value
|
||||
}
|
||||
|
||||
// saturating, csr is missing
|
||||
// it seems sat() (and its shortcut +| and -|) in SpinalHDL don't do what I need
|
||||
// for unsigned substraction (no way to tell the difference between overflow
|
||||
// and underflow unless going signed, I think)
|
||||
def fun_satsub8u(a: Bits, b: Bits) : Bits = {
|
||||
val s = (B"1'b0" ## a).asSInt -^ (B"1'b0" ## b).asSInt // -^ will keep 10 bits
|
||||
// if sign bit set -> underflow, else if bit eight set -> overflow
|
||||
val r = ((s(9).asUInt === 1) ? (B"8'x00") | ((s(8).asUInt === 1) ? (B"8'xFF") | (s(7 downto 0).asBits)))
|
||||
|
||||
r // return value
|
||||
}
|
||||
|
||||
def fun_kadd8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = (rs1( 7 downto 0).asSInt +| rs2( 7 downto 0).asSInt).asBits.resize(8)
|
||||
val b1 = (rs1(15 downto 8).asSInt +| rs2(15 downto 8).asSInt).asBits.resize(8)
|
||||
val b2 = (rs1(23 downto 16).asSInt +| rs2(23 downto 16).asSInt).asBits.resize(8)
|
||||
val b3 = (rs1(31 downto 24).asSInt +| rs2(31 downto 24).asSInt).asBits.resize(8)
|
||||
|
||||
b3 ## b2 ## b1 ## b0 // return value
|
||||
}
|
||||
def fun_ukadd8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = (rs1( 7 downto 0).asUInt +| rs2( 7 downto 0).asUInt).asBits.resize(8)
|
||||
val b1 = (rs1(15 downto 8).asUInt +| rs2(15 downto 8).asUInt).asBits.resize(8)
|
||||
val b2 = (rs1(23 downto 16).asUInt +| rs2(23 downto 16).asUInt).asBits.resize(8)
|
||||
val b3 = (rs1(31 downto 24).asUInt +| rs2(31 downto 24).asUInt).asBits.resize(8)
|
||||
|
||||
b3 ## b2 ## b1 ## b0 // return value
|
||||
}
|
||||
def fun_ksub8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = (rs1( 7 downto 0).asSInt -| rs2( 7 downto 0).asSInt).asBits.resize(8)
|
||||
val b1 = (rs1(15 downto 8).asSInt -| rs2(15 downto 8).asSInt).asBits.resize(8)
|
||||
val b2 = (rs1(23 downto 16).asSInt -| rs2(23 downto 16).asSInt).asBits.resize(8)
|
||||
val b3 = (rs1(31 downto 24).asSInt -| rs2(31 downto 24).asSInt).asBits.resize(8)
|
||||
|
||||
b3 ## b2 ## b1 ## b0 // return value
|
||||
}
|
||||
def fun_uksub8(rs1: Bits, rs2: Bits) : Bits = {
|
||||
val b0 = fun_satsub8u(rs1( 7 downto 0), rs2( 7 downto 0)).asBits
|
||||
val b1 = fun_satsub8u(rs1(15 downto 8), rs2(15 downto 8)).asBits
|
||||
val b2 = fun_satsub8u(rs1(23 downto 16), rs2(23 downto 16)).asBits
|
||||
val b3 = fun_satsub8u(rs1(31 downto 24), rs2(31 downto 24)).asBits
|
||||
|
||||
b3 ## b2 ## b1 ## b0 // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class GoblinPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import GoblinPlugin._
|
||||
object IS_Goblin extends Stageable(Bool)
|
||||
object Goblin_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_Goblin -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_Goblin -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
IS_Goblin -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_Goblin -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
|
||||
BYPASSABLE_MEMORY_STAGE -> True,
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_Goblin -> True
|
||||
)
|
||||
def UKADD8_KEY = M"0011100----------000-----1110111"
|
||||
def UKSUB8_KEY = M"0011101----------000-----1110111"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_Goblin, False)
|
||||
decoderService.add(List(
|
||||
UKADD8_KEY -> (binaryActions ++ List(GoblinCtrl -> GoblinCtrlEnum.CTRL_pdpikadd8, GoblinCtrlpdpikadd8 -> GoblinCtrlpdpikadd8Enum.CTRL_UKADD8)),
|
||||
UKSUB8_KEY -> (binaryActions ++ List(GoblinCtrl -> GoblinCtrlEnum.CTRL_pdpikadd8, GoblinCtrlpdpikadd8 -> GoblinCtrlpdpikadd8Enum.CTRL_UKSUB8))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
val val_pdpikadd8 = input(GoblinCtrlpdpikadd8).mux(
|
||||
GoblinCtrlpdpikadd8Enum.CTRL_UKADD8 -> fun_ukadd8(input(SRC1), input(SRC2)).asBits,
|
||||
GoblinCtrlpdpikadd8Enum.CTRL_UKSUB8 -> fun_uksub8(input(SRC1), input(SRC2)).asBits
|
||||
) // mux pdpikadd8
|
||||
insert(Goblin_FINAL_OUTPUT) := val_pdpikadd8.asBits
|
||||
} // execute plug newArea
|
||||
val injectionStage = if(earlyInjection) execute else memory
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_Goblin)) {
|
||||
output(REGFILE_WRITE_DATA) := input(Goblin_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
// WARNING: this is auto-generated code!
|
||||
// See https://github.com/rdolbeau/VexRiscvBPluginGenerator/
|
||||
package vexriscv.plugin
|
||||
import spinal.core._
|
||||
import vexriscv.{Stageable, DecoderService, VexRiscv}
|
||||
object Goblin2cPlugin {
|
||||
object Goblin2cCtrlEnum extends SpinalEnum(binarySequential) {
|
||||
val CTRL_UFMA8VxV = newElement()
|
||||
}
|
||||
object Goblin2cCtrl extends Stageable(Goblin2cCtrlEnum())
|
||||
// Prologue
|
||||
|
||||
def fun_ufma8vxv(rs1: Bits, rs2: Bits, rs3: Bits, low: Bool) : Bits = {
|
||||
val al = low ? rs2( 7 downto 0) | rs2(31 downto 24)
|
||||
|
||||
val h0 = (rs1( 7 downto 0).asUInt * al.asUInt).asBits
|
||||
val h1 = (rs1(15 downto 8).asUInt * al.asUInt).asBits
|
||||
val h2 = (rs1(23 downto 16).asUInt * al.asUInt).asBits
|
||||
val h3 = (rs1(31 downto 24).asUInt * al.asUInt).asBits
|
||||
|
||||
//rs3 ## h3(15 downto 8) ## h2(15 downto 8) ## h1(15 downto 8) ## h0(15 downto 8) // return value
|
||||
|
||||
//var r0 = ((h0 ## B"8'x00").asUInt + h0.asUInt + h0(15 downto 7).asUInt).asBits
|
||||
//var r1 = ((h1 ## B"8'x00").asUInt + h1.asUInt + h1(15 downto 7).asUInt).asBits
|
||||
//var r2 = ((h2 ## B"8'x00").asUInt + h2.asUInt + h2(15 downto 7).asUInt).asBits
|
||||
//var r3 = ((h3 ## B"8'x00").asUInt + h3.asUInt + h3(15 downto 7).asUInt).asBits
|
||||
|
||||
//rs3 ## r3(23 downto 16) ## r2(23 downto 16) ## r1(23 downto 16) ## r0(23 downto 16) // return value
|
||||
|
||||
rs3 ## h3 ## h2 ## h1 ## h0
|
||||
}
|
||||
|
||||
def fun_ufma8vxv2(input: Bits) : Bits = {
|
||||
//val rs3 = input(63 downto 32)
|
||||
val rs3 = input(95 downto 64)
|
||||
val h3 = input(63 downto 48)
|
||||
val h2 = input(47 downto 32)
|
||||
val h1 = input(31 downto 16)
|
||||
val h0 = input(15 downto 0)
|
||||
|
||||
var r0 = ((h0 ## B"8'x00").asUInt + h0.asUInt + h0(15 downto 7).asUInt).asBits
|
||||
var r1 = ((h1 ## B"8'x00").asUInt + h1.asUInt + h1(15 downto 7).asUInt).asBits
|
||||
var r2 = ((h2 ## B"8'x00").asUInt + h2.asUInt + h2(15 downto 7).asUInt).asBits
|
||||
var r3 = ((h3 ## B"8'x00").asUInt + h3.asUInt + h3(15 downto 7).asUInt).asBits
|
||||
|
||||
//val f0 = (input( 7 downto 0).asUInt +| rs3( 7 downto 0).asUInt).asBits.resize(8)
|
||||
//val f1 = (input(15 downto 8).asUInt +| rs3(15 downto 8).asUInt).asBits.resize(8)
|
||||
//val f2 = (input(23 downto 16).asUInt +| rs3(23 downto 16).asUInt).asBits.resize(8)
|
||||
//val f3 = (input(31 downto 24).asUInt +| rs3(31 downto 24).asUInt).asBits.resize(8)
|
||||
|
||||
val f0 = (r0(23 downto 16).asUInt +| rs3( 7 downto 0).asUInt).asBits.resize(8)
|
||||
val f1 = (r1(23 downto 16).asUInt +| rs3(15 downto 8).asUInt).asBits.resize(8)
|
||||
val f2 = (r2(23 downto 16).asUInt +| rs3(23 downto 16).asUInt).asBits.resize(8)
|
||||
val f3 = (r3(23 downto 16).asUInt +| rs3(31 downto 24).asUInt).asBits.resize(8)
|
||||
|
||||
f3 ## f2 ## f1 ## f0 // return value
|
||||
}
|
||||
|
||||
// End prologue
|
||||
} // object Plugin
|
||||
class Goblin2cPlugin(earlyInjection : Boolean = true) extends Plugin[VexRiscv] {
|
||||
import Goblin2cPlugin._
|
||||
object IS_Goblin2c extends Stageable(Bool)
|
||||
object Goblin2c_FINAL_OUTPUT extends Stageable(Bits(32 bits))
|
||||
object Goblin2c_INTERMEDIATE_UFMA8VxV96 extends Stageable(Bits(96 bits))
|
||||
override def setup(pipeline: VexRiscv): Unit = {
|
||||
import pipeline.config._
|
||||
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> False,
|
||||
BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection),
|
||||
RS1_USE -> True,
|
||||
IS_Goblin2c -> True
|
||||
)
|
||||
val binaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> False,
|
||||
BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection),
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
IS_Goblin2c -> True
|
||||
)
|
||||
val unaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> False,
|
||||
BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection),
|
||||
RS1_USE -> True,
|
||||
IS_Goblin2c -> True
|
||||
)
|
||||
val ternaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.RS,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> False,
|
||||
BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection),
|
||||
RS1_USE -> True,
|
||||
RS2_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_Goblin2c -> True
|
||||
)
|
||||
val immTernaryActions = List[(Stageable[_ <: BaseType],Any)](
|
||||
SRC1_CTRL -> Src1CtrlEnum.RS,
|
||||
SRC2_CTRL -> Src2CtrlEnum.IMI,
|
||||
SRC3_CTRL -> Src3CtrlEnum.RS,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> False,
|
||||
BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection),
|
||||
RS1_USE -> True,
|
||||
RS3_USE -> True,
|
||||
IS_Goblin2c -> True
|
||||
)
|
||||
def UFMA8VxV_KEY = M"11001-0----------000----01110111"
|
||||
val decoderService = pipeline.service(classOf[DecoderService])
|
||||
decoderService.addDefault(IS_Goblin2c, False)
|
||||
decoderService.add(List(
|
||||
UFMA8VxV_KEY -> (ternaryActions ++ List(Goblin2cCtrl -> Goblin2cCtrlEnum.CTRL_UFMA8VxV))
|
||||
))
|
||||
} // override def setup
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
import pipeline.config._
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
insert(Goblin2c_INTERMEDIATE_UFMA8VxV96) := fun_ufma8vxv(input(SRC1), input(SRC2), input(SRC3), (input(INSTRUCTION)(26).asUInt === 1)).asBits
|
||||
} // execute plug newArea
|
||||
memory plug new Area{
|
||||
import memory._
|
||||
insert(Goblin2c_FINAL_OUTPUT) := fun_ufma8vxv2(input(Goblin2c_INTERMEDIATE_UFMA8VxV96)).asBits
|
||||
} // memory plug newArea
|
||||
val injectionStage = if(earlyInjection) memory else writeBack
|
||||
injectionStage plug new Area {
|
||||
import injectionStage._
|
||||
when (arbitration.isValid && input(IS_Goblin2c)) {
|
||||
output(REGFILE_WRITE_DATA) := input(Goblin2c_FINAL_OUTPUT)
|
||||
} // when input is
|
||||
} // injectionStage plug newArea
|
||||
} // override def build
|
||||
} // class Plugin
|
||||
|
|
@ -136,14 +136,14 @@ module VexRiscv (
|
|||
wire [15:0] dataCache_1_io_mem_cmd_payload_mask;
|
||||
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
|
||||
wire dataCache_1_io_mem_cmd_payload_last;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_9;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_10;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_11;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_12;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_13;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_14;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_15;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_16;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_17;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_18;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_19;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_20;
|
||||
wire [51:0] _zz_memory_MUL_LOW;
|
||||
wire [51:0] _zz_memory_MUL_LOW_1;
|
||||
wire [51:0] _zz_memory_MUL_LOW_2;
|
||||
|
|
@ -153,14 +153,10 @@ module VexRiscv (
|
|||
wire [49:0] _zz_memory_MUL_LOW_6;
|
||||
wire [51:0] _zz_memory_MUL_LOW_7;
|
||||
wire [49:0] _zz_memory_MUL_LOW_8;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_1;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_2;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_3;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_4;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_5;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_6;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_7;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_8;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_1;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_2;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_3;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_4;
|
||||
wire [31:0] _zz_execute_SHIFT_RIGHT;
|
||||
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
|
||||
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
|
||||
|
|
@ -402,6 +398,34 @@ module VexRiscv (
|
|||
wire [0:0] _zz_execute_GoblinPlugin_val_pdpikadd8_39;
|
||||
wire [0:0] _zz_execute_GoblinPlugin_val_pdpikadd8_40;
|
||||
wire [7:0] _zz_execute_GoblinPlugin_val_pdpikadd8_41;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_1;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_2;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_3;
|
||||
wire [15:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_4;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_5;
|
||||
wire [8:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_6;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_1;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_2;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_3;
|
||||
wire [15:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_4;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_5;
|
||||
wire [8:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_6;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_1;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_2;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_3;
|
||||
wire [15:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_4;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_5;
|
||||
wire [8:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_6;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_1;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_2;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_3;
|
||||
wire [15:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_4;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_5;
|
||||
wire [8:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_6;
|
||||
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
|
||||
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
|
||||
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
|
||||
|
|
@ -418,7 +442,7 @@ module VexRiscv (
|
|||
wire [51:0] memory_MUL_LOW;
|
||||
wire [31:0] execute_BRANCH_CALC;
|
||||
wire execute_BRANCH_DO;
|
||||
wire [63:0] execute_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
wire [95:0] execute_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
wire [31:0] execute_Goblin_FINAL_OUTPUT;
|
||||
wire [31:0] execute_CG6_FINAL_OUTPUT;
|
||||
wire [31:0] execute_SHIFT_RIGHT;
|
||||
|
|
@ -532,7 +556,7 @@ module VexRiscv (
|
|||
reg [31:0] decode_RS1;
|
||||
wire [31:0] writeBack_Goblin2c_FINAL_OUTPUT;
|
||||
wire writeBack_IS_Goblin2c;
|
||||
wire [63:0] memory_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
wire [95:0] memory_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
wire [31:0] memory_Goblin_FINAL_OUTPUT;
|
||||
wire memory_IS_Goblin;
|
||||
wire [0:0] execute_GoblinCtrlpdpikadd8;
|
||||
|
|
@ -1011,21 +1035,25 @@ module VexRiscv (
|
|||
wire [9:0] _zz_execute_GoblinPlugin_val_pdpikadd8_15;
|
||||
reg [31:0] execute_GoblinPlugin_val_pdpikadd8;
|
||||
wire when_Goblin_l591;
|
||||
wire [7:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
wire [7:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
wire [31:0] _zz_memory_Goblin2c_FINAL_OUTPUT;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_1;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_2;
|
||||
wire when_UInt_l119_4;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_3;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_4;
|
||||
wire when_UInt_l119_5;
|
||||
wire [15:0] _zz_memory_Goblin2c_FINAL_OUTPUT_1;
|
||||
wire [15:0] _zz_memory_Goblin2c_FINAL_OUTPUT_2;
|
||||
wire [15:0] _zz_memory_Goblin2c_FINAL_OUTPUT_3;
|
||||
wire [15:0] _zz_memory_Goblin2c_FINAL_OUTPUT_4;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_5;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_6;
|
||||
wire when_UInt_l119_6;
|
||||
wire when_UInt_l119_4;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_7;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_8;
|
||||
wire when_UInt_l119_5;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_9;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_10;
|
||||
wire when_UInt_l119_6;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_11;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_12;
|
||||
wire when_UInt_l119_7;
|
||||
wire when_Goblin2c_l115;
|
||||
wire when_Goblin2c_l139;
|
||||
reg HazardSimplePlugin_src0Hazard;
|
||||
reg HazardSimplePlugin_src1Hazard;
|
||||
reg HazardSimplePlugin_src2Hazard;
|
||||
|
|
@ -1255,7 +1283,7 @@ module VexRiscv (
|
|||
wire when_Pipeline_l124_67;
|
||||
reg [31:0] execute_to_memory_Goblin_FINAL_OUTPUT;
|
||||
wire when_Pipeline_l124_68;
|
||||
reg [63:0] execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
reg [95:0] execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
wire when_Pipeline_l124_69;
|
||||
reg execute_to_memory_BRANCH_DO;
|
||||
wire when_Pipeline_l124_70;
|
||||
|
|
@ -1399,14 +1427,14 @@ module VexRiscv (
|
|||
(* ram_style = "distributed" *) reg [31:0] RegFileOddEvenPlugin_regFileEven [0:15] /* verilator public */ ;
|
||||
(* ram_style = "distributed" *) reg [31:0] RegFileOddEvenPlugin_regFileOdd [0:15] /* verilator public */ ;
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_10 = _zz_memory_Goblin2c_FINAL_OUTPUT_8;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_9 = _zz_memory_Goblin2c_FINAL_OUTPUT_10;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_12 = _zz_memory_Goblin2c_FINAL_OUTPUT_6;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_11 = _zz_memory_Goblin2c_FINAL_OUTPUT_12;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_14 = _zz_memory_Goblin2c_FINAL_OUTPUT_4;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_14 = _zz_memory_Goblin2c_FINAL_OUTPUT_12;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_13 = _zz_memory_Goblin2c_FINAL_OUTPUT_14;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_16 = _zz_memory_Goblin2c_FINAL_OUTPUT_2;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_16 = _zz_memory_Goblin2c_FINAL_OUTPUT_10;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_15 = _zz_memory_Goblin2c_FINAL_OUTPUT_16;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_18 = _zz_memory_Goblin2c_FINAL_OUTPUT_8;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_17 = _zz_memory_Goblin2c_FINAL_OUTPUT_18;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_20 = _zz_memory_Goblin2c_FINAL_OUTPUT_6;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_19 = _zz_memory_Goblin2c_FINAL_OUTPUT_20;
|
||||
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
|
||||
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
|
||||
assign _zz_memory_MUL_LOW_2 = 52'h0;
|
||||
|
|
@ -1416,14 +1444,10 @@ module VexRiscv (
|
|||
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
|
||||
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
|
||||
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_1 = _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_2;
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_2 = (execute_SRC1[31 : 24] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_3 = _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_4;
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_4 = (execute_SRC1[23 : 16] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_5 = _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_6;
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_6 = (execute_SRC1[15 : 8] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_7 = _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_8;
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_8 = (execute_SRC1[7 : 0] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_1 = (execute_SRC1[31 : 24] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_2 = (execute_SRC1[23 : 16] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_3 = (execute_SRC1[15 : 8] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_4 = (execute_SRC1[7 : 0] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96);
|
||||
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
|
||||
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
|
||||
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
|
||||
|
|
@ -1479,6 +1503,34 @@ module VexRiscv (
|
|||
assign _zz_execute_GoblinPlugin_val_pdpikadd8_31 = _zz_execute_GoblinPlugin_val_pdpikadd8_12[7 : 0];
|
||||
assign _zz_execute_GoblinPlugin_val_pdpikadd8_37 = _zz_execute_GoblinPlugin_val_pdpikadd8_9[7 : 0];
|
||||
assign _zz_execute_GoblinPlugin_val_pdpikadd8_41 = _zz_execute_GoblinPlugin_val_pdpikadd8_6[7 : 0];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5 = _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_1 = (_zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_2 + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_5);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_2 = ({_zz_memory_Goblin2c_FINAL_OUTPUT_4,8'h0} + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_3);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_4;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_3 = {8'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_4};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_4[15 : 7];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_5 = {15'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_6};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7 = _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_1 = (_zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_2 + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_5);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_2 = ({_zz_memory_Goblin2c_FINAL_OUTPUT_3,8'h0} + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_3);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_3;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_3 = {8'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_4};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_3[15 : 7];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_5 = {15'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_6};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9 = _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_1 = (_zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_2 + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_5);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_2 = ({_zz_memory_Goblin2c_FINAL_OUTPUT_2,8'h0} + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_3);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_2;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_3 = {8'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_4};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_2[15 : 7];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_5 = {15'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_6};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11 = _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_1 = (_zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_2 + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_5);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_2 = ({_zz_memory_Goblin2c_FINAL_OUTPUT_1,8'h0} + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_3);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_3 = {8'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_4};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_1[15 : 7];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_5 = {15'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_6};
|
||||
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
|
||||
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
|
||||
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
|
||||
|
|
@ -2810,11 +2862,11 @@ module VexRiscv (
|
|||
end
|
||||
`endif
|
||||
|
||||
assign memory_Goblin2c_FINAL_OUTPUT = {{{_zz_memory_Goblin2c_FINAL_OUTPUT_9,_zz_memory_Goblin2c_FINAL_OUTPUT_11},_zz_memory_Goblin2c_FINAL_OUTPUT_13},_zz_memory_Goblin2c_FINAL_OUTPUT_15};
|
||||
assign memory_Goblin2c_FINAL_OUTPUT = {{{_zz_memory_Goblin2c_FINAL_OUTPUT_13,_zz_memory_Goblin2c_FINAL_OUTPUT_15},_zz_memory_Goblin2c_FINAL_OUTPUT_17},_zz_memory_Goblin2c_FINAL_OUTPUT_19};
|
||||
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
|
||||
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
|
||||
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
|
||||
assign execute_Goblin2c_INTERMEDIATE_UFMA8VxV64 = {{{{execute_SRC3,_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_1[15 : 8]},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_3[15 : 8]},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_5[15 : 8]},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_7[15 : 8]};
|
||||
assign execute_Goblin2c_INTERMEDIATE_UFMA8VxV96 = {{{{execute_SRC3,_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_1},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_2},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_3},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_4};
|
||||
assign execute_Goblin_FINAL_OUTPUT = execute_GoblinPlugin_val_pdpikadd8;
|
||||
assign execute_CG6_FINAL_OUTPUT = _zz_execute_CG6_FINAL_OUTPUT;
|
||||
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
|
||||
|
|
@ -3053,7 +3105,7 @@ module VexRiscv (
|
|||
|
||||
assign writeBack_Goblin2c_FINAL_OUTPUT = memory_to_writeBack_Goblin2c_FINAL_OUTPUT;
|
||||
assign writeBack_IS_Goblin2c = memory_to_writeBack_IS_Goblin2c;
|
||||
assign memory_Goblin2c_INTERMEDIATE_UFMA8VxV64 = execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
assign memory_Goblin2c_INTERMEDIATE_UFMA8VxV96 = execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
assign memory_Goblin_FINAL_OUTPUT = execute_to_memory_Goblin_FINAL_OUTPUT;
|
||||
assign memory_IS_Goblin = execute_to_memory_IS_Goblin;
|
||||
assign execute_GoblinCtrlpdpikadd8 = _zz_execute_GoblinCtrlpdpikadd8;
|
||||
|
|
@ -3164,7 +3216,7 @@ module VexRiscv (
|
|||
end
|
||||
endcase
|
||||
end
|
||||
if(when_Goblin2c_l115) begin
|
||||
if(when_Goblin2c_l139) begin
|
||||
_zz_decode_RS3_5 = writeBack_Goblin2c_FINAL_OUTPUT;
|
||||
end
|
||||
end
|
||||
|
|
@ -4308,49 +4360,53 @@ module VexRiscv (
|
|||
end
|
||||
|
||||
assign when_Goblin_l591 = (memory_arbitration_isValid && memory_IS_Goblin);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64 = ((execute_INSTRUCTION[26] == 1'b1) ? execute_SRC2[7 : 0] : execute_SRC2[31 : 24]);
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT = memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[63 : 32];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_1 = ({1'b0,memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[7 : 0]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[7 : 0]});
|
||||
assign when_UInt_l119_4 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_1[8 : 8]);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96 = ((execute_INSTRUCTION[26] == 1'b1) ? execute_SRC2[7 : 0] : execute_SRC2[31 : 24]);
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[95 : 64];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_1 = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[63 : 48];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_2 = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[47 : 32];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_3 = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[31 : 16];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_4 = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[15 : 0];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_5 = ({1'b0,_zz__zz_memory_Goblin2c_FINAL_OUTPUT_5[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[7 : 0]});
|
||||
assign when_UInt_l119_4 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_5[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_4) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_2 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_2 = _zz_memory_Goblin2c_FINAL_OUTPUT_1[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_3 = ({1'b0,memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[15 : 8]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[15 : 8]});
|
||||
assign when_UInt_l119_5 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_3[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_5) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_4 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_3[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_5 = ({1'b0,memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[23 : 16]});
|
||||
assign when_UInt_l119_6 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_5[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_6) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_6 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_5[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_7 = ({1'b0,memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[31 : 24]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[31 : 24]});
|
||||
assign when_UInt_l119_7 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_7[8 : 8]);
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_7 = ({1'b0,_zz__zz_memory_Goblin2c_FINAL_OUTPUT_7[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[15 : 8]});
|
||||
assign when_UInt_l119_5 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_7[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_7) begin
|
||||
if(when_UInt_l119_5) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_8 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_8 = _zz_memory_Goblin2c_FINAL_OUTPUT_7[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign when_Goblin2c_l115 = (writeBack_arbitration_isValid && writeBack_IS_Goblin2c);
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_9 = ({1'b0,_zz__zz_memory_Goblin2c_FINAL_OUTPUT_9[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[23 : 16]});
|
||||
assign when_UInt_l119_6 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_9[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_6) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_10 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_10 = _zz_memory_Goblin2c_FINAL_OUTPUT_9[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_11 = ({1'b0,_zz__zz_memory_Goblin2c_FINAL_OUTPUT_11[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[31 : 24]});
|
||||
assign when_UInt_l119_7 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_11[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_7) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_12 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_12 = _zz_memory_Goblin2c_FINAL_OUTPUT_11[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign when_Goblin2c_l139 = (writeBack_arbitration_isValid && writeBack_IS_Goblin2c);
|
||||
always @(*) begin
|
||||
HazardSimplePlugin_src0Hazard = 1'b0;
|
||||
if(when_HazardSimplePlugin_l91) begin
|
||||
|
|
@ -5242,7 +5298,7 @@ module VexRiscv (
|
|||
execute_to_memory_Goblin_FINAL_OUTPUT <= execute_Goblin_FINAL_OUTPUT;
|
||||
end
|
||||
if(when_Pipeline_l124_68) begin
|
||||
execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV64 <= execute_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV96 <= execute_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
end
|
||||
if(when_Pipeline_l124_69) begin
|
||||
execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
|
||||
|
|
|
|||
|
|
@ -136,14 +136,14 @@ module VexRiscv (
|
|||
wire [15:0] dataCache_1_io_mem_cmd_payload_mask;
|
||||
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
|
||||
wire dataCache_1_io_mem_cmd_payload_last;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_9;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_10;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_11;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_12;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_13;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_14;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_15;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_16;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_17;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_18;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_19;
|
||||
wire [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_20;
|
||||
wire [51:0] _zz_memory_MUL_LOW;
|
||||
wire [51:0] _zz_memory_MUL_LOW_1;
|
||||
wire [51:0] _zz_memory_MUL_LOW_2;
|
||||
|
|
@ -153,14 +153,10 @@ module VexRiscv (
|
|||
wire [49:0] _zz_memory_MUL_LOW_6;
|
||||
wire [51:0] _zz_memory_MUL_LOW_7;
|
||||
wire [49:0] _zz_memory_MUL_LOW_8;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_1;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_2;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_3;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_4;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_5;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_6;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_7;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_8;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_1;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_2;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_3;
|
||||
wire [15:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_4;
|
||||
wire [31:0] _zz_execute_SHIFT_RIGHT;
|
||||
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
|
||||
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
|
||||
|
|
@ -402,6 +398,34 @@ module VexRiscv (
|
|||
wire [0:0] _zz_execute_GoblinPlugin_val_pdpikadd8_39;
|
||||
wire [0:0] _zz_execute_GoblinPlugin_val_pdpikadd8_40;
|
||||
wire [7:0] _zz_execute_GoblinPlugin_val_pdpikadd8_41;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_1;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_2;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_3;
|
||||
wire [15:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_4;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_5;
|
||||
wire [8:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_6;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_1;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_2;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_3;
|
||||
wire [15:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_4;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_5;
|
||||
wire [8:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_6;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_1;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_2;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_3;
|
||||
wire [15:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_4;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_5;
|
||||
wire [8:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_6;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_1;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_2;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_3;
|
||||
wire [15:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_4;
|
||||
wire [23:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_5;
|
||||
wire [8:0] _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_6;
|
||||
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
|
||||
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
|
||||
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
|
||||
|
|
@ -418,7 +442,7 @@ module VexRiscv (
|
|||
wire [51:0] memory_MUL_LOW;
|
||||
wire [31:0] execute_BRANCH_CALC;
|
||||
wire execute_BRANCH_DO;
|
||||
wire [63:0] execute_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
wire [95:0] execute_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
wire [31:0] execute_Goblin_FINAL_OUTPUT;
|
||||
wire [31:0] execute_CG6_FINAL_OUTPUT;
|
||||
wire [31:0] execute_SHIFT_RIGHT;
|
||||
|
|
@ -532,7 +556,7 @@ module VexRiscv (
|
|||
reg [31:0] decode_RS1;
|
||||
wire [31:0] writeBack_Goblin2c_FINAL_OUTPUT;
|
||||
wire writeBack_IS_Goblin2c;
|
||||
wire [63:0] memory_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
wire [95:0] memory_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
wire [31:0] memory_Goblin_FINAL_OUTPUT;
|
||||
wire memory_IS_Goblin;
|
||||
wire [0:0] execute_GoblinCtrlpdpikadd8;
|
||||
|
|
@ -1011,21 +1035,25 @@ module VexRiscv (
|
|||
wire [9:0] _zz_execute_GoblinPlugin_val_pdpikadd8_15;
|
||||
reg [31:0] execute_GoblinPlugin_val_pdpikadd8;
|
||||
wire when_Goblin_l591;
|
||||
wire [7:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
wire [7:0] _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
wire [31:0] _zz_memory_Goblin2c_FINAL_OUTPUT;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_1;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_2;
|
||||
wire when_UInt_l119_4;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_3;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_4;
|
||||
wire when_UInt_l119_5;
|
||||
wire [15:0] _zz_memory_Goblin2c_FINAL_OUTPUT_1;
|
||||
wire [15:0] _zz_memory_Goblin2c_FINAL_OUTPUT_2;
|
||||
wire [15:0] _zz_memory_Goblin2c_FINAL_OUTPUT_3;
|
||||
wire [15:0] _zz_memory_Goblin2c_FINAL_OUTPUT_4;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_5;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_6;
|
||||
wire when_UInt_l119_6;
|
||||
wire when_UInt_l119_4;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_7;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_8;
|
||||
wire when_UInt_l119_5;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_9;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_10;
|
||||
wire when_UInt_l119_6;
|
||||
wire [8:0] _zz_memory_Goblin2c_FINAL_OUTPUT_11;
|
||||
reg [7:0] _zz_memory_Goblin2c_FINAL_OUTPUT_12;
|
||||
wire when_UInt_l119_7;
|
||||
wire when_Goblin2c_l115;
|
||||
wire when_Goblin2c_l139;
|
||||
reg HazardSimplePlugin_src0Hazard;
|
||||
reg HazardSimplePlugin_src1Hazard;
|
||||
reg HazardSimplePlugin_src2Hazard;
|
||||
|
|
@ -1255,7 +1283,7 @@ module VexRiscv (
|
|||
wire when_Pipeline_l124_67;
|
||||
reg [31:0] execute_to_memory_Goblin_FINAL_OUTPUT;
|
||||
wire when_Pipeline_l124_68;
|
||||
reg [63:0] execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
reg [95:0] execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
wire when_Pipeline_l124_69;
|
||||
reg execute_to_memory_BRANCH_DO;
|
||||
wire when_Pipeline_l124_70;
|
||||
|
|
@ -1399,14 +1427,14 @@ module VexRiscv (
|
|||
(* ram_style = "distributed" *) reg [31:0] RegFileOddEvenPlugin_regFileEven [0:15] /* verilator public */ ;
|
||||
(* ram_style = "distributed" *) reg [31:0] RegFileOddEvenPlugin_regFileOdd [0:15] /* verilator public */ ;
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_10 = _zz_memory_Goblin2c_FINAL_OUTPUT_8;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_9 = _zz_memory_Goblin2c_FINAL_OUTPUT_10;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_12 = _zz_memory_Goblin2c_FINAL_OUTPUT_6;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_11 = _zz_memory_Goblin2c_FINAL_OUTPUT_12;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_14 = _zz_memory_Goblin2c_FINAL_OUTPUT_4;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_14 = _zz_memory_Goblin2c_FINAL_OUTPUT_12;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_13 = _zz_memory_Goblin2c_FINAL_OUTPUT_14;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_16 = _zz_memory_Goblin2c_FINAL_OUTPUT_2;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_16 = _zz_memory_Goblin2c_FINAL_OUTPUT_10;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_15 = _zz_memory_Goblin2c_FINAL_OUTPUT_16;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_18 = _zz_memory_Goblin2c_FINAL_OUTPUT_8;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_17 = _zz_memory_Goblin2c_FINAL_OUTPUT_18;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_20 = _zz_memory_Goblin2c_FINAL_OUTPUT_6;
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_19 = _zz_memory_Goblin2c_FINAL_OUTPUT_20;
|
||||
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
|
||||
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
|
||||
assign _zz_memory_MUL_LOW_2 = 52'h0;
|
||||
|
|
@ -1416,14 +1444,10 @@ module VexRiscv (
|
|||
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
|
||||
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
|
||||
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_1 = _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_2;
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_2 = (execute_SRC1[31 : 24] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_3 = _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_4;
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_4 = (execute_SRC1[23 : 16] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_5 = _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_6;
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_6 = (execute_SRC1[15 : 8] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_7 = _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_8;
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_8 = (execute_SRC1[7 : 0] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_1 = (execute_SRC1[31 : 24] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_2 = (execute_SRC1[23 : 16] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_3 = (execute_SRC1[15 : 8] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_4 = (execute_SRC1[7 : 0] * _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96);
|
||||
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
|
||||
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
|
||||
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
|
||||
|
|
@ -1479,6 +1503,34 @@ module VexRiscv (
|
|||
assign _zz_execute_GoblinPlugin_val_pdpikadd8_31 = _zz_execute_GoblinPlugin_val_pdpikadd8_12[7 : 0];
|
||||
assign _zz_execute_GoblinPlugin_val_pdpikadd8_37 = _zz_execute_GoblinPlugin_val_pdpikadd8_9[7 : 0];
|
||||
assign _zz_execute_GoblinPlugin_val_pdpikadd8_41 = _zz_execute_GoblinPlugin_val_pdpikadd8_6[7 : 0];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5 = _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_1 = (_zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_2 + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_5);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_2 = ({_zz_memory_Goblin2c_FINAL_OUTPUT_4,8'h0} + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_3);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_4;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_3 = {8'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_4};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_4[15 : 7];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_5 = {15'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_5_6};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7 = _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_1 = (_zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_2 + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_5);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_2 = ({_zz_memory_Goblin2c_FINAL_OUTPUT_3,8'h0} + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_3);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_3;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_3 = {8'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_4};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_3[15 : 7];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_5 = {15'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_7_6};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9 = _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_1 = (_zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_2 + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_5);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_2 = ({_zz_memory_Goblin2c_FINAL_OUTPUT_2,8'h0} + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_3);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_2;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_3 = {8'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_4};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_2[15 : 7];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_5 = {15'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_9_6};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11 = _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_1 = (_zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_2 + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_5);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_2 = ({_zz_memory_Goblin2c_FINAL_OUTPUT_1,8'h0} + _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_3);
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_1;
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_3 = {8'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_4};
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_1[15 : 7];
|
||||
assign _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_5 = {15'd0, _zz__zz_memory_Goblin2c_FINAL_OUTPUT_11_6};
|
||||
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
|
||||
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
|
||||
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
|
||||
|
|
@ -2810,11 +2862,11 @@ module VexRiscv (
|
|||
end
|
||||
`endif
|
||||
|
||||
assign memory_Goblin2c_FINAL_OUTPUT = {{{_zz_memory_Goblin2c_FINAL_OUTPUT_9,_zz_memory_Goblin2c_FINAL_OUTPUT_11},_zz_memory_Goblin2c_FINAL_OUTPUT_13},_zz_memory_Goblin2c_FINAL_OUTPUT_15};
|
||||
assign memory_Goblin2c_FINAL_OUTPUT = {{{_zz_memory_Goblin2c_FINAL_OUTPUT_13,_zz_memory_Goblin2c_FINAL_OUTPUT_15},_zz_memory_Goblin2c_FINAL_OUTPUT_17},_zz_memory_Goblin2c_FINAL_OUTPUT_19};
|
||||
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
|
||||
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
|
||||
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
|
||||
assign execute_Goblin2c_INTERMEDIATE_UFMA8VxV64 = {{{{execute_SRC3,_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_1[15 : 8]},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_3[15 : 8]},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_5[15 : 8]},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64_7[15 : 8]};
|
||||
assign execute_Goblin2c_INTERMEDIATE_UFMA8VxV96 = {{{{execute_SRC3,_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_1},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_2},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_3},_zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96_4};
|
||||
assign execute_Goblin_FINAL_OUTPUT = execute_GoblinPlugin_val_pdpikadd8;
|
||||
assign execute_CG6_FINAL_OUTPUT = _zz_execute_CG6_FINAL_OUTPUT;
|
||||
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
|
||||
|
|
@ -3053,7 +3105,7 @@ module VexRiscv (
|
|||
|
||||
assign writeBack_Goblin2c_FINAL_OUTPUT = memory_to_writeBack_Goblin2c_FINAL_OUTPUT;
|
||||
assign writeBack_IS_Goblin2c = memory_to_writeBack_IS_Goblin2c;
|
||||
assign memory_Goblin2c_INTERMEDIATE_UFMA8VxV64 = execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
assign memory_Goblin2c_INTERMEDIATE_UFMA8VxV96 = execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
assign memory_Goblin_FINAL_OUTPUT = execute_to_memory_Goblin_FINAL_OUTPUT;
|
||||
assign memory_IS_Goblin = execute_to_memory_IS_Goblin;
|
||||
assign execute_GoblinCtrlpdpikadd8 = _zz_execute_GoblinCtrlpdpikadd8;
|
||||
|
|
@ -3164,7 +3216,7 @@ module VexRiscv (
|
|||
end
|
||||
endcase
|
||||
end
|
||||
if(when_Goblin2c_l115) begin
|
||||
if(when_Goblin2c_l139) begin
|
||||
_zz_decode_RS3_5 = writeBack_Goblin2c_FINAL_OUTPUT;
|
||||
end
|
||||
end
|
||||
|
|
@ -4308,49 +4360,53 @@ module VexRiscv (
|
|||
end
|
||||
|
||||
assign when_Goblin_l591 = (memory_arbitration_isValid && memory_IS_Goblin);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV64 = ((execute_INSTRUCTION[26] == 1'b1) ? execute_SRC2[7 : 0] : execute_SRC2[31 : 24]);
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT = memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[63 : 32];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_1 = ({1'b0,memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[7 : 0]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[7 : 0]});
|
||||
assign when_UInt_l119_4 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_1[8 : 8]);
|
||||
assign _zz_execute_Goblin2c_INTERMEDIATE_UFMA8VxV96 = ((execute_INSTRUCTION[26] == 1'b1) ? execute_SRC2[7 : 0] : execute_SRC2[31 : 24]);
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[95 : 64];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_1 = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[63 : 48];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_2 = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[47 : 32];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_3 = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[31 : 16];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_4 = memory_Goblin2c_INTERMEDIATE_UFMA8VxV96[15 : 0];
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_5 = ({1'b0,_zz__zz_memory_Goblin2c_FINAL_OUTPUT_5[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[7 : 0]});
|
||||
assign when_UInt_l119_4 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_5[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_4) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_2 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_2 = _zz_memory_Goblin2c_FINAL_OUTPUT_1[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_3 = ({1'b0,memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[15 : 8]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[15 : 8]});
|
||||
assign when_UInt_l119_5 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_3[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_5) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_4 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_4 = _zz_memory_Goblin2c_FINAL_OUTPUT_3[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_5 = ({1'b0,memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[23 : 16]});
|
||||
assign when_UInt_l119_6 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_5[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_6) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_6 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_6 = _zz_memory_Goblin2c_FINAL_OUTPUT_5[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_7 = ({1'b0,memory_Goblin2c_INTERMEDIATE_UFMA8VxV64[31 : 24]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[31 : 24]});
|
||||
assign when_UInt_l119_7 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_7[8 : 8]);
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_7 = ({1'b0,_zz__zz_memory_Goblin2c_FINAL_OUTPUT_7[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[15 : 8]});
|
||||
assign when_UInt_l119_5 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_7[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_7) begin
|
||||
if(when_UInt_l119_5) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_8 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_8 = _zz_memory_Goblin2c_FINAL_OUTPUT_7[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign when_Goblin2c_l115 = (writeBack_arbitration_isValid && writeBack_IS_Goblin2c);
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_9 = ({1'b0,_zz__zz_memory_Goblin2c_FINAL_OUTPUT_9[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[23 : 16]});
|
||||
assign when_UInt_l119_6 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_9[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_6) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_10 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_10 = _zz_memory_Goblin2c_FINAL_OUTPUT_9[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign _zz_memory_Goblin2c_FINAL_OUTPUT_11 = ({1'b0,_zz__zz_memory_Goblin2c_FINAL_OUTPUT_11[23 : 16]} + {1'b0,_zz_memory_Goblin2c_FINAL_OUTPUT[31 : 24]});
|
||||
assign when_UInt_l119_7 = (|_zz_memory_Goblin2c_FINAL_OUTPUT_11[8 : 8]);
|
||||
always @(*) begin
|
||||
if(when_UInt_l119_7) begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_12 = 8'hff;
|
||||
end else begin
|
||||
_zz_memory_Goblin2c_FINAL_OUTPUT_12 = _zz_memory_Goblin2c_FINAL_OUTPUT_11[7 : 0];
|
||||
end
|
||||
end
|
||||
|
||||
assign when_Goblin2c_l139 = (writeBack_arbitration_isValid && writeBack_IS_Goblin2c);
|
||||
always @(*) begin
|
||||
HazardSimplePlugin_src0Hazard = 1'b0;
|
||||
if(when_HazardSimplePlugin_l91) begin
|
||||
|
|
@ -5242,7 +5298,7 @@ module VexRiscv (
|
|||
execute_to_memory_Goblin_FINAL_OUTPUT <= execute_Goblin_FINAL_OUTPUT;
|
||||
end
|
||||
if(when_Pipeline_l124_68) begin
|
||||
execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV64 <= execute_Goblin2c_INTERMEDIATE_UFMA8VxV64;
|
||||
execute_to_memory_Goblin2c_INTERMEDIATE_UFMA8VxV96 <= execute_Goblin2c_INTERMEDIATE_UFMA8VxV96;
|
||||
end
|
||||
if(when_Pipeline_l124_69) begin
|
||||
execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
|
||||
|
|
|
|||
Loading…
Reference in New Issue