mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-05-27 22:48:30 +00:00
move fb_dma, fb_video to common
This commit is contained in:
Romain Dolbeau
parent
f2da1f1163
commit
904a248264
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@ -1 +1 @@
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Subproject commit 72ea9145acf639632a2d3bfa383b28e41a307c41
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Subproject commit 747e95cb9c4574776c42fa53a9ed0e07e6bd9ea6
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@ -1,43 +0,0 @@
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from math import log2
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from migen import *
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from litedram.frontend.dma import LiteDRAMDMAReader;
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# LiteDRAMDFBMAReader --------------------------------------------------------------------------------
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# Hardwire the loop, uses control signals instead of CSRs
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class LiteDRAMFBDMAReader(LiteDRAMDMAReader):
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def __init__(self, port, fifo_depth=16, default_base=0, default_length=0):
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LiteDRAMDMAReader.__init__(self = self, port = port, fifo_depth = fifo_depth, fifo_buffered = True, with_csr = False)
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self.enable = Signal(reset = 0)
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self.base = Signal(32, reset = default_base)
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self.length = Signal(32, reset = default_length)
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shift = log2_int(self.port.data_width//8)
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base = Signal(self.port.address_width)
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length = Signal(self.port.address_width)
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offset = Signal(self.port.address_width, reset = 0)
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self.comb += base.eq(self.base[shift:])
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self.comb += length.eq(self.length[shift:])
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fsm = FSM(reset_state="IDLE")
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fsm = ResetInserter()(fsm)
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self.submodules.fsm = fsm
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self.comb += fsm.reset.eq(~self.enable)
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fsm.act("IDLE",
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NextValue(offset, 0),
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NextState("RUN"),
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)
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fsm.act("RUN",
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self.sink.valid.eq(1),
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self.sink.last.eq(offset == (length - 1)),
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self.sink.address.eq(base + offset),
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If(self.sink.ready,
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NextValue(offset, offset + 1),
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If(self.sink.last,
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NextValue(offset, 0)
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)
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)
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)
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@ -1,199 +0,0 @@
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import os
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import math
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from migen import *
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from migen.genlib.cdc import MultiReg
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import stream
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from litex.soc.cores.code_tmds import TMDSEncoder
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from litex.build.io import SDROutput, DDROutput
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from litex.soc.cores.video import *
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video_timing_nohwcursor_layout = [
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# Synchronization signals.
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("hsync", 1),
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("vsync", 1),
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("de", 1),
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("inframe", 1),
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# Extended/Optional synchronization signals.
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("hres", hbits),
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("vres", vbits),
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("hcount", hbits),
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("vcount", vbits),
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]
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video_timing_hwcursor_layout = [
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# Synchronization signals.
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("hsync", 1),
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("vsync", 1),
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("de", 1),
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("inframe", 1),
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("hwcursor", 1),
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("hwcursorx", 5),
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("hwcursory", 5),
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# Extended/Optional synchronization signals.
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("hres", hbits),
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("vres", vbits),
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("hcount", hbits),
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("vcount", vbits),
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]
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# FB Video Timing Generator ---------------------------------------------------------------------------
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# Same as the normal one except (a) _enable isn't a CSR
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class FBVideoTimingGenerator(Module, AutoCSR):
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def __init__(self, default_video_timings="800x600@60Hz", hwcursor=False):
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# Check / Get Video Timings (can be str or dict)
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if isinstance(default_video_timings, str):
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try:
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self.video_timings = vt = video_timings[default_video_timings]
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except KeyError:
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msg = [f"Video Timings {default_video_timings} not supported, availables:"]
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for video_timing in video_timings.keys():
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msg.append(f" - {video_timing} / {video_timings[video_timing]['pix_clk']/1e6:3.2f}MHz.")
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raise ValueError("\n".join(msg))
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else:
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self.video_timings = vt = default_video_timings
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# MMAP Control/Status Registers.
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self.enable = Signal() # external control signal
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self._hres = CSRStorage(hbits, vt["h_active"])
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self._hsync_start = CSRStorage(hbits, vt["h_active"] + vt["h_sync_offset"])
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self._hsync_end = CSRStorage(hbits, vt["h_active"] + vt["h_sync_offset"] + vt["h_sync_width"])
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self._hscan = CSRStorage(hbits, vt["h_active"] + vt["h_blanking"])
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self._vres = CSRStorage(vbits, vt["v_active"])
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self._vsync_start = CSRStorage(vbits, vt["v_active"] + vt["v_sync_offset"])
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self._vsync_end = CSRStorage(vbits, vt["v_active"] + vt["v_sync_offset"] + vt["v_sync_width"])
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self._vscan = CSRStorage(vbits, vt["v_active"] + vt["v_blanking"])
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self._hres_start = Signal(hbits, reset = 0)
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self._hres_end = Signal(hbits, reset = vt["h_active"])
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self._vres_start = Signal(hbits, reset = 0)
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self._vres_end = Signal(hbits, reset = vt["v_active"])
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# Video Timing Source
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if (hwcursor):
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self.source = source = stream.Endpoint(video_timing_hwcursor_layout)
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_hwcursor_x = Signal(12) # 12 out of 16 is enough
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_hwcursor_y = Signal(12) # 12 out of 16 is enough
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self.hwcursor_x = Signal(12)
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self.hwcursor_y = Signal(12)
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self.specials += MultiReg(self.hwcursor_x, _hwcursor_x)
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self.specials += MultiReg(self.hwcursor_y, _hwcursor_y)
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else:
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self.source = source = stream.Endpoint(video_timing_nohwcursor_layout)
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# # #
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# Resynchronize Horizontal Timings to Video clock domain.
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self.hres = hres = Signal(hbits)
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self.hsync_start = hsync_start = Signal(hbits)
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self.hsync_end = hsync_end = Signal(hbits)
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self.hscan = hscan = Signal(hbits)
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self.specials += MultiReg(self._hres.storage, hres)
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self.specials += MultiReg(self._hsync_start.storage, hsync_start)
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self.specials += MultiReg(self._hsync_end.storage, hsync_end)
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self.specials += MultiReg(self._hscan.storage, hscan)
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# Resynchronize Vertical Timings to Video clock domain.
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self.vres = vres = Signal(vbits)
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self.vsync_start = vsync_start = Signal(vbits)
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self.vsync_end = vsync_end = Signal(vbits)
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self.vscan = vscan = Signal(vbits)
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self.specials += MultiReg(self._vres.storage, vres)
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self.specials += MultiReg(self._vsync_start.storage, vsync_start)
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self.specials += MultiReg(self._vsync_end.storage, vsync_end)
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self.specials += MultiReg(self._vscan.storage, vscan)
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self.hres_start = hres_start = Signal(hbits)
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self.hres_end = hres_end = Signal(hbits)
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self.vres_start = vres_start = Signal(vbits)
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self.vres_end = vres_end = Signal(vbits)
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self.specials += MultiReg(self._hres_start, hres_start)
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self.specials += MultiReg(self._hres_end, hres_end)
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self.specials += MultiReg(self._vres_start, vres_start)
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self.specials += MultiReg(self._vres_end, vres_end)
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# Generate timings.
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# whether we're in the visible frame
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hactive = Signal()
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vactive = Signal()
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# whether we're in the picture (including non-visible part of frame for windowboxing)
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hinframe = Signal()
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vinframe = Signal()
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fsm = FSM(reset_state="IDLE")
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fsm = ResetInserter()(fsm)
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self.submodules.fsm = fsm
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self.comb += fsm.reset.eq(~self.enable)
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fsm.act("IDLE",
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NextValue(hactive, 0),
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NextValue(vactive, 0),
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NextValue(hinframe, 0),
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NextValue(vinframe, 0),
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NextValue(source.hres, hres),
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NextValue(source.vres, vres),
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NextValue(source.hcount, 0),
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NextValue(source.vcount, 0),
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NextState("RUN")
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)
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self.comb += source.de.eq(hactive & vactive) # DE when both HActive and VActive.
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self.comb += source.inframe.eq(hinframe & vinframe) # InFrame when both HInFrame and VInFrame.
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self.sync += source.first.eq((source.hcount == 0) & (source.vcount == 0)),
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self.sync += source.last.eq( (source.hcount == hscan) & (source.vcount == vscan)),
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fsm.act("RUN",
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source.valid.eq(1),
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If(source.ready,
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# Increment HCount.
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NextValue(source.hcount, source.hcount + 1),
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# Generate HActive / HSync.
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If(source.hcount == hres_start, NextValue(hactive, 1)), # Start of HActive.
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If(source.hcount == hres_end, NextValue(hactive, 0)), # End of HActive.
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If(source.hcount == 0, NextValue(hinframe, 1)), # Start of HInFrame.
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If(source.hcount == hres, NextValue(hinframe, 0)), # End of HInFrame.
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If(source.hcount == hsync_start, NextValue(source.hsync, 1)), # Start of HSync.
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If(source.hcount == hsync_end, NextValue(source.hsync, 0)), # End of HSync.
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# End of HScan.
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If(source.hcount == hscan,
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# Reset HCount.
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NextValue(source.hcount, 0),
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# Increment VCount.
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NextValue(source.vcount, source.vcount + 1),
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# Generate VActive / VSync.
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If(source.vcount == vres_start, NextValue(vactive, 1)), # Start of VActive.
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If(source.vcount == vres_end, NextValue(vactive, 0)), # End of VActive.
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If(source.vcount == 0, NextValue(vinframe, 1)), # Start of VInFrame.
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If(source.vcount == vres, NextValue(vinframe, 0)), # End of VInFrame.
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If(source.vcount == vsync_start, NextValue(source.vsync, 1)), # Start of VSync.
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If(source.vcount == vsync_end, NextValue(source.vsync, 0)), # End of VSync.
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# End of VScan.
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If(source.vcount == vscan,
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# Reset VCount.
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NextValue(source.vcount, 0),
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)
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)
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)
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)
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# fixme: likely more efficient to have two bits (X, Y) to check if we're in the area, rather than two compare...
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# could also handle the offsets w/o two subtractions
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# but how to deal with changing value ??? copy them at the beginning of frame ?
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if (hwcursor):
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h_offset = Signal(hbits)
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v_offset = Signal(vbits)
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self.comb += [
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h_offset.eq(source.hcount - hres_start),
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v_offset.eq(source.vcount - vres_start),
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]
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self.sync += source.hwcursor.eq((h_offset >= _hwcursor_x) &
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(h_offset < (_hwcursor_x+32)) &
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(v_offset >= _hwcursor_y) &
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(v_offset < (_hwcursor_y+32)))
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self.sync += source.hwcursorx.eq(_hwcursor_x - h_offset)
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self.sync += source.hwcursory.eq(_hwcursor_y - v_offset)
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