mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-06-10 12:29:35 +00:00
Move Vex to a 128-bit Wishbone, and add a bypass to access a dedicated memory port with a 128-bits datapath. Speeds up scrolling quite nicely.
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@ -5,6 +5,9 @@ from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litedram.common import LiteDRAMNativePort
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from litedram.frontend.wishbone import LiteDRAMWishbone2Native
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class GoblinAccel(Module): # AutoCSR ?
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class GoblinAccel(Module): # AutoCSR ?
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def __init__(self, soc):
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def __init__(self, soc):
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platform = soc.platform
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platform = soc.platform
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@ -157,12 +160,92 @@ class GoblinAccel(Module): # AutoCSR ?
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]
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]
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#led0 = platform.request("user_led", 0)
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#led0 = platform.request("user_led", 0)
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#self.comb += led0.eq(~local_reset)
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#self.comb += led0.eq(~local_reset) # Vex connection to the primary bus
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self.ibus = ibus = wishbone.Interface()
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self.ibus = ibus = wishbone.Interface()
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self.dbus = dbus = wishbone.Interface()
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#self.dbus = dbus = wishbone.Interface()
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vex_reset = Signal()
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vex_reset = Signal()
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dbus_raw = wishbone.Interface(data_width=128, adr_width=28) # wide interface from the Vex, master
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dbus_sys = wishbone.Interface(data_width=128, adr_width=28) # wide interface to system wishbone
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dbus_mem = wishbone.Interface(data_width=128, adr_width=28) # wide interface for direct memory access
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self.dbus = dbus_sys
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#masters = {}
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#masters["VexRiscv_AccelFB"] = dbus_raw
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##slaves["VexSystemAccess"] = dbus
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##regions["VexSystemAccess"] = SoCRegion(origin=soc.mem_map.get("goblin_bt", None), size=0x00100000, cached=False)
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##slaves["VexMemoryAccess"] = dbus_mem
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##regions["VexSystemAccess"] = SoCRegion(origin=soc.mem_map.get("main_ram", None), size=0x10000000, cached=True)
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#function_VexSystemAccess = lambda x: (x[24:28] != 0x8)
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#function_VexMemoryAccess = lambda x: (x[24:28] == 0x8)
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##function_VexSystemAccess = lambda x: (True)
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##function_VexMemoryAccess = lambda x: (False)
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#slaves = [
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# (function_VexSystemAccess, dbus_sys),
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# (function_VexMemoryAccess, dbus_mem),
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#]
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#self.submodules.crossbar = wishbone.Crossbar(
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# masters = masters.values(),
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# slaves = slaves,
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# register = False,
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# timeout_cycles = None
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#)
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#self.submodules.shared = wishbone.InterconnectShared(
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# masters = masters.values(),
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# slaves = slaves,
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# register = False,
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# timeout_cycles = None
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#)
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self.comb += [
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If((dbus_raw.adr[24:28] == 0x8),
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dbus_sys.cyc.eq(0),
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dbus_sys.stb.eq(0),
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dbus_mem.cyc.eq(dbus_raw.cyc),
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dbus_mem.stb.eq(dbus_raw.stb),
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dbus_raw.ack.eq(dbus_mem.ack),
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dbus_raw.err.eq(dbus_mem.err),
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dbus_raw.dat_r.eq(dbus_mem.dat_r),
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).Else(
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dbus_sys.cyc.eq(dbus_raw.cyc),
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dbus_sys.stb.eq(dbus_raw.stb),
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dbus_mem.cyc.eq(0),
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dbus_mem.stb.eq(0),
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dbus_raw.ack.eq(dbus_sys.ack),
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dbus_raw.err.eq(dbus_sys.err),
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dbus_raw.dat_r.eq(dbus_sys.dat_r),
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),
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dbus_sys.dat_w.eq(dbus_raw.dat_w),
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dbus_mem.dat_w.eq(dbus_raw.dat_w),
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dbus_sys.we.eq(dbus_raw.we),
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dbus_mem.we.eq(dbus_raw.we),
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dbus_sys.adr.eq(dbus_raw.adr),
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dbus_mem.adr.eq(dbus_raw.adr),
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dbus_sys.sel.eq(dbus_raw.sel),
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dbus_mem.sel.eq(dbus_raw.sel),
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dbus_sys.cti.eq(dbus_raw.cti),
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dbus_mem.cti.eq(dbus_raw.cti),
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dbus_sys.bte.eq(dbus_raw.bte),
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dbus_mem.bte.eq(dbus_raw.bte),
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]
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# now connect the memory
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# memory port
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port = soc.sdram.crossbar.get_port()
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assert(port.data_width == 128)
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self.submodules.wb2native = LiteDRAMWishbone2Native(
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wishbone = dbus_mem,
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port = port,
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base_address = soc.bus.regions["main_ram"].origin
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)
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self.comb += vex_reset.eq(ResetSignal("sys") | local_reset)
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self.comb += vex_reset.eq(ResetSignal("sys") | local_reset)
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self.specials += Instance(self.get_netlist_name(),
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self.specials += Instance(self.get_netlist_name(),
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i_clk = ClockSignal("sys"),
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i_clk = ClockSignal("sys"),
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@ -178,17 +261,17 @@ class GoblinAccel(Module): # AutoCSR ?
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i_iBusWishbone_ERR = ibus.err,
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i_iBusWishbone_ERR = ibus.err,
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o_iBusWishbone_CTI = ibus.cti,
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o_iBusWishbone_CTI = ibus.cti,
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o_iBusWishbone_BTE = ibus.bte,
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o_iBusWishbone_BTE = ibus.bte,
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o_dBusWishbone_CYC = dbus.cyc,
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o_dBusWishbone_CYC = dbus_raw.cyc,
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o_dBusWishbone_STB = dbus.stb,
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o_dBusWishbone_STB = dbus_raw.stb,
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i_dBusWishbone_ACK = dbus.ack,
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i_dBusWishbone_ACK = dbus_raw.ack,
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o_dBusWishbone_WE = dbus.we,
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o_dBusWishbone_WE = dbus_raw.we,
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o_dBusWishbone_ADR = dbus.adr,
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o_dBusWishbone_ADR = dbus_raw.adr,
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i_dBusWishbone_DAT_MISO = dbus.dat_r,
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i_dBusWishbone_DAT_MISO = dbus_raw.dat_r,
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o_dBusWishbone_DAT_MOSI = dbus.dat_w,
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o_dBusWishbone_DAT_MOSI = dbus_raw.dat_w,
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o_dBusWishbone_SEL = dbus.sel,
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o_dBusWishbone_SEL = dbus_raw.sel,
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i_dBusWishbone_ERR = dbus.err,
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i_dBusWishbone_ERR = dbus_raw.err,
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o_dBusWishbone_CTI = dbus.cti,
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o_dBusWishbone_CTI = dbus_raw.cti,
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o_dBusWishbone_BTE = dbus.bte,)
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o_dBusWishbone_BTE = dbus_raw.bte,)
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self.add_sources(platform)
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self.add_sources(platform)
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@ -320,7 +320,7 @@ class NuBusFPGA(SoCCore):
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self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
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self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
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nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
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nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
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wishbone_slave_nubus = wishbone.Interface(data_width=self.bus.data_width)
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wishbone_slave_nubus = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus")
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self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus", force_delay=6) # force delay needed to avoid back-to-back transaction running into issue https://github.com/alexforencich/verilog-wishbone/issues/4
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self.submodules.nubus = nubus_full.NuBus(platform=platform,
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self.submodules.nubus = nubus_full.NuBus(platform=platform,
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wb_read=self.wishbone_master_nubus,
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wb_read=self.wishbone_master_nubus,
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wb_write=nubus_writemaster_sys,
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wb_write=nubus_writemaster_sys,
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