mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-05-27 22:48:30 +00:00
sync non-sampling with sampling code
This commit is contained in:
Romain Dolbeau
parent
45de956195
commit
b935541f61
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@ -7,8 +7,12 @@ import litex
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from litex.soc.interconnect import wishbone
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class NuBus(Module):
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def __init__(self, platform, wb_read, wb_write, wb_dma, cd_nubus="nubus", cd_nubus90="nubus90"):
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def __init__(self, soc,
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burst_size, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo,
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wb_read, wb_write, wb_dma,
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cd_nubus="nubus", cd_nubus90="nubus90"):
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platform = soc.platform
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self.add_sources(platform)
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#led0 = platform.request("user_led", 0)
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@ -18,11 +22,11 @@ class NuBus(Module):
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# slave
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tmo_oe = Signal() # output enable
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tm0_i_n = Signal()
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tm0_o_n = Signal()
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tm0_o_n = Signal(reset = 1)
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tm1_i_n = Signal()
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tm1_o_n = Signal()
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tm1_o_n = Signal(reset = 1)
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ack_i_n = Signal()
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ack_o_n = Signal()
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ack_o_n = Signal(reset = 1)
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ad_oe = Signal()
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ad_i_n = Signal(32)
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@ -31,12 +35,12 @@ class NuBus(Module):
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id_i_n = Signal(4)
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start_i_n = Signal()
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start_o_n = Signal() # master via master_oe
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start_o_n = Signal(reset = 1) # master via master_oe
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# master
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rqst_oe = Signal()
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rqst_i_n = Signal()
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rqst_o_n = Signal()
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rqst_o_n = Signal(reset = 1)
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# sampled signals, exposing the value of the register acquired on the falling edge
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# they can change every cycle *on falling edge*
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@ -46,6 +50,7 @@ class NuBus(Module):
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sampled_start = Signal()
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sampled_ack = Signal()
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sampled_ad = Signal(32)
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sampled_ad_byterev = Signal(32)
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# master
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sampled_rqst = Signal()
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@ -62,6 +67,10 @@ class NuBus(Module):
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processed_ad[23:32].eq(Cat(sampled_ad[23], Signal(8, reset = 0xf0)))), # 24 bits, a.k.a 22 bits of words
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processed_super_ad[0:28].eq(sampled_ad[0:28]),
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processed_super_ad[28:32].eq(Signal(4, reset = 0x8)),
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sampled_ad_byterev[ 0: 8].eq(sampled_ad[24:32]),
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sampled_ad_byterev[ 8:16].eq(sampled_ad[16:24]),
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sampled_ad_byterev[16:24].eq(sampled_ad[ 8:16]),
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sampled_ad_byterev[24:32].eq(sampled_ad[ 0: 8]),
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]
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# decoded signals, exposing decoded results from the sampled signals
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@ -232,16 +241,59 @@ class NuBus(Module):
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]
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self.submodules.dma_fsm = dma_fsm = ClockDomainsRenamer(cd_nubus)(FSM(reset_state="Reset"))
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ctr = Signal(2) # burst counter
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burst = Signal()
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burst_we = Signal()
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data_width = burst_size * 4
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data_width_bits = burst_size * 32
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blk_addr_width = 32 - log2_int(data_width) # 27 for burst_size == 8, 28 for burst_size == 4
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fifo_addr = Signal(blk_addr_width)
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fifo_blk_addr = Signal(blk_addr_width)
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fifo_buffer = Signal(data_width_bits)
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tosbus_fifo_dout = Record(soc.tosbus_layout)
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self.comb += tosbus_fifo_dout.raw_bits().eq(tosbus_fifo.dout)
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tosbus_fifo_dout_data_byterev = Signal(data_width_bits)
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tosbus_fifo_dout_bytereversal_stmts = [ tosbus_fifo_dout_data_byterev[k*32+j*8:k*32+j*8+8].eq(tosbus_fifo_dout.data[k*32+32-j*8-8:k*32+32-j*8]) for k in range(burst_size) for j in range(4) ]
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self.comb += tosbus_fifo_dout_bytereversal_stmts
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fromsbus_req_fifo_dout = Record(soc.fromsbus_req_layout)
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self.comb += fromsbus_req_fifo_dout.raw_bits().eq(fromsbus_req_fifo.dout)
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fromsbus_fifo_din = Record(soc.fromsbus_layout)
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self.comb += fromsbus_fifo.din.eq(fromsbus_fifo_din.raw_bits())
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dma_fsm.act("Reset",
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NextState("Idle")
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)
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dma_fsm.act("Idle",
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If(wb_dma.cyc & wb_dma.stb & ~sampled_rqst, # we need the bus and it's not being requested
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NextValue(burst, 0),
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If(owning_bus, # we own the bus, skip arbitration
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NextState("AdrCycle"),
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).Else( # go for arbitration
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NextState("Arbitration"),
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),
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).Elif(tosbus_fifo.readable & ~sampled_rqst,
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NextValue(burst, 1),
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NextValue(burst_we, 1),
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NextValue(fifo_addr, tosbus_fifo_dout.address[(32-blk_addr_width):32]),
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If(owning_bus, # we own the bus, skip arbitration
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NextState("Burst4AdrCycle"),
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).Else( # go for arbitration
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NextState("Arbitration"),
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)
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).Elif(fromsbus_req_fifo.readable & fromsbus_fifo.writable & ~sampled_rqst,
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NextValue(burst, 1),
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NextValue(burst_we, 0),
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NextValue(fifo_addr, fromsbus_req_fifo_dout.dmaaddress[(32-blk_addr_width):32]),
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NextValue(fifo_blk_addr, fromsbus_req_fifo_dout.blkaddress),
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If(owning_bus, # we own the bus, skip arbitration
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NextState("Burst4AdrCycle"),
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).Else( # go for arbitration
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NextState("Arbitration"),
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)
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)
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)
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dma_fsm.act("Arbitration",
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@ -256,7 +308,11 @@ class NuBus(Module):
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rqst_o_n.eq(0),
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If(grant & ~decoded_busy, # I'm now 'owner'
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NextValue(owning_bus, 1),
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NextState("AdrCycle"),
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If(burst,
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NextState("Burst4AdrCycle"),
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).Else(
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NextState("AdrCycle"),
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),
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)
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)
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dma_fsm.act("AdrCycle",
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@ -307,6 +363,110 @@ class NuBus(Module):
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NextState("FinishCycle"),
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)
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)
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dma_fsm.act("Burst4AdrCycle",
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start_arbitration.eq(0),
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master_oe.eq(1), # for start
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tmo_oe.eq(1), # for tm0, tm1, ack
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ad_oe.eq(1), # for write address
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start_o_n.eq(0),
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tm0_o_n.eq(1), # burst
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tm1_o_n.eq(~burst_we),
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ad_o_n[0].eq(1), # burst
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ad_o_n[1].eq(0), # burst
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ad_o_n[2].eq(0), # burst == 4
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ad_o_n[3].eq(1), # burst == 4
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ad_o_n[4:32].eq(~fifo_addr),
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ack_o_n.eq(1),
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NextValue(ctr, 0),
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If(burst_we,
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NextState("Burst4DatCycleTM0"),
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).Else(
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NextState("Burst4ReadWaitForTM0"),
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)
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)
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dma_fsm.act("Burst4ReadWaitForTM0",
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master_oe.eq(1), # for start
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start_o_n.eq(1), # start finished, but still need to be driven
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If(sampled_ack, # oups
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fromsbus_req_fifo.re.eq(1), # remove request to avoid infinite repeat
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#NextValue(led0, 1),
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#NextValue(led1, 1),
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NextState("FinishCycle"),
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).Elif(sampled_tm0,
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Case(ctr, {
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#0x0: NextValue(fifo_buffer[ 0: 32], sampled_ad),
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#0x1: NextValue(fifo_buffer[32: 64], sampled_ad),
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#0x2: NextValue(fifo_buffer[64: 96], sampled_ad),
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##0x3: NextValue(fifo_buffer[96:128], sampled_ad),
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0x0: NextValue(fifo_buffer[ 0: 32], sampled_ad_byterev),
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0x1: NextValue(fifo_buffer[32: 64], sampled_ad_byterev),
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0x2: NextValue(fifo_buffer[64: 96], sampled_ad_byterev),
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#0x3: NextValue(fifo_buffer[96:128], sampled_ad_byterev),
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}),
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NextValue(ctr, ctr + 1),
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If(ctr == 0x2, # burst next-to-last
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NextState("Burst4ReadWaitForAck"),
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).Else(
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NextState("Burst4ReadWaitForTM0"),
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)
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)
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)
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dma_fsm.act("Burst4ReadWaitForAck",
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master_oe.eq(1), # for start
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start_o_n.eq(1), # start finished, but still need to be driven
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If(sampled_ack,
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fromsbus_req_fifo.re.eq(1), # remove request
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fromsbus_fifo.we.eq(1),
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fromsbus_fifo_din.blkaddress.eq(fifo_blk_addr),
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#fromsbus_fifo_din.data.eq(Cat(fifo_buffer[0:96], sampled_ad)), # we use sampled_ad directly for 96:128
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fromsbus_fifo_din.data.eq(Cat(fifo_buffer[0:96], sampled_ad_byterev)), # we use sampled_ad directly for 96:128
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# fixme: check status ??? (tm0 and tm1 should be active for no-error)
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#NextValue(led0, (~sampled_tm0 | ~sampled_tm1)),
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NextState("FinishCycle"),
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)
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)
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dma_fsm.act("Burst4DatCycleTM0",
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master_oe.eq(1), # for start
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ad_oe.eq(1), # for write data
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start_o_n.eq(1), # start finished, but still need to be driven
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Case(ctr, {
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#0x0: ad_o_n.eq(~tosbus_fifo_dout.data[ 0: 32]),
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#0x1: ad_o_n.eq(~tosbus_fifo_dout.data[32: 64]),
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#0x2: ad_o_n.eq(~tosbus_fifo_dout.data[64: 96]),
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##0x3: ad_o_n.eq(~tosbus_fifo_dout.data[96:128]),
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0x0: ad_o_n.eq(~tosbus_fifo_dout_data_byterev[ 0: 32]),
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0x1: ad_o_n.eq(~tosbus_fifo_dout_data_byterev[32: 64]),
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0x2: ad_o_n.eq(~tosbus_fifo_dout_data_byterev[64: 96]),
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#0x3: ad_o_n.eq(~tosbus_fifo_dout_data_byterev[96:128]),
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}),
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If(sampled_ack, # oups
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#NextValue(led0, 1),
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#NextValue(led1, 1),
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tosbus_fifo.re.eq(1), # remove FIFO entry to avoid infinite repeat
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NextState("FinishCycle"),
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).Elif(sampled_tm0,
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NextValue(ctr, ctr + 1),
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If(ctr == 0x2, # burst next-to-last
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NextState("Burst4DatCycleAck"),
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).Else(
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NextState("Burst4DatCycleTM0"),
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)
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)
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)
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dma_fsm.act("Burst4DatCycleAck",
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master_oe.eq(1), # for start
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ad_oe.eq(1), # for write data
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start_o_n.eq(1), # start finished, but still need to be driven
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#ad_o_n.eq(~tosbus_fifo_dout.data[96:128]), # last word
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ad_o_n.eq(~tosbus_fifo_dout_data_byterev[96:128]), # last word
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If(sampled_ack,
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tosbus_fifo.re.eq(1), # remove FIFO entry at last
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# fixme: check status ??? (tm0 and tm1 should be active for no-error)
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#NextValue(led0, (~sampled_tm0 | ~sampled_tm1)),
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NextState("FinishCycle"),
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)
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)
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# stuff at this end so we don't use the signals inadvertantly
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