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https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-12-22 10:29:53 +00:00
preliminary burst support for DMA
This commit is contained in:
Romain Dolbeau
parent
5e7e7d5e2c
commit
c0fbdca5d3
@ -7,12 +7,16 @@ import litex
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from litex.soc.interconnect import wishbone
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class NuBus(Module):
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def __init__(self, platform, wb_read, wb_write, wb_dma, cd_nubus="nubus", cd_nubus90="nubus90"):
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def __init__(self, soc,
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burst_size, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo,
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wb_read, wb_write, wb_dma,
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cd_nubus="nubus", cd_nubus90="nubus90"):
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platform = soc.platform
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self.add_sources(platform)
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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led0 = platform.request("user_led", 0)
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led1 = platform.request("user_led", 1)
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nub_clk = ClockSignal(cd_nubus)
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nub_resetn = ~ResetSignal(cd_nubus)
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@ -321,16 +325,56 @@ class NuBus(Module):
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]
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self.submodules.dma_fsm = dma_fsm = ClockDomainsRenamer(cd_nubus)(FSM(reset_state="Reset"))
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ctr = Signal(2) # burst counter
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burst = Signal()
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burst_we = Signal()
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data_width = burst_size * 4
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data_width_bits = burst_size * 32
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blk_addr_width = 32 - log2_int(data_width) # 27 for burst_size == 8, 28 for burst_size == 4
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fifo_addr = Signal(blk_addr_width)
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fifo_blk_addr = Signal(blk_addr_width)
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fifo_buffer = Signal(data_width_bits)
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tosbus_fifo_dout = Record(soc.tosbus_layout)
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self.comb += tosbus_fifo_dout.raw_bits().eq(tosbus_fifo.dout)
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fromsbus_req_fifo_dout = Record(soc.fromsbus_req_layout)
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self.comb += fromsbus_req_fifo_dout.raw_bits().eq(fromsbus_req_fifo.dout)
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fromsbus_fifo_din = Record(soc.fromsbus_layout)
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self.comb += fromsbus_fifo.din.eq(fromsbus_fifo_din.raw_bits())
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dma_fsm.act("Reset",
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NextState("Idle")
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)
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dma_fsm.act("Idle",
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If(wb_dma.cyc & wb_dma.stb & ~sampled_rqst, # we need the bus and it's not being requested
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NextValue(burst, 0),
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If(owning_bus, # we own the bus, skip arbitration
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NextState("AdrCycle"),
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).Else( # go for arbitration
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NextState("Arbitration"),
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),
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).Elif(tosbus_fifo.readable & ~sampled_rqst,
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NextValue(burst, 1),
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NextValue(burst_we, 1),
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NextValue(fifo_addr, tosbus_fifo_dout.address[(32-blk_addr_width):32]),
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If(owning_bus, # we own the bus, skip arbitration
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NextState("Burst4AdrCycle"),
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).Else( # go for arbitration
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NextState("Arbitration"),
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)
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).Elif(fromsbus_req_fifo.readable & fromsbus_fifo.writable & ~sampled_rqst,
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NextValue(burst, 1),
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NextValue(burst_we, 0),
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NextValue(fifo_addr, fromsbus_req_fifo_dout.dmaaddress[(32-blk_addr_width):32]),
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NextValue(fifo_blk_addr, fromsbus_req_fifo_dout.blkaddress),
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If(owning_bus, # we own the bus, skip arbitration
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NextState("Burst4AdrCycle"),
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).Else( # go for arbitration
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NextState("Arbitration"),
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)
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)
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)
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dma_fsm.act("Arbitration",
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@ -345,7 +389,11 @@ class NuBus(Module):
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rqst_o_n.eq(0),
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If(grant & ~decoded_busy, # I'm now 'owner'
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NextValue(owning_bus, 1),
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NextState("AdrCycle"),
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If(burst,
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NextState("Burst4AdrCycle"),
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).Else(
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NextState("AdrCycle"),
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),
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)
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)
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dma_fsm.act("AdrCycle",
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@ -374,6 +422,7 @@ class NuBus(Module):
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If(sampled_ack,
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wb_dma.ack.eq(1),
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# fixme: check status ??? (tm0 and tm1 should be active for no-error)
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NextValue(led0, (~sampled_tm0 | ~sampled_tm1)),
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NextState("FinishCycle"),
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)
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)
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@ -393,6 +442,101 @@ class NuBus(Module):
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If(sampled_ack,
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wb_dma.ack.eq(1),
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# fixme: check status ??? (tm0 and tm1 should be active for no-error)
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NextValue(led0, (~sampled_tm0 | ~sampled_tm1)),
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NextState("FinishCycle"),
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)
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)
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dma_fsm.act("Burst4AdrCycle",
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start_arbitration.eq(0),
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master_oe.eq(1), # for start
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tmo_oe.eq(1), # for tm0, tm1, ack
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ad_oe.eq(1), # for write address
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start_o_n.eq(0),
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tm0_o_n.eq(1), # burst
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tm1_o_n.eq(~burst_we),
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ad_o_n[0].eq(1), # burst
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ad_o_n[1].eq(0), # burst
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ad_o_n[2].eq(0), # burst == 4
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ad_o_n[3].eq(1), # burst == 4
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ad_o_n[4:32].eq(~fifo_addr),
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ack_o_n.eq(1),
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NextValue(ctr, 0),
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If(burst_we,
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NextState("Burst4DatCycleTM0"),
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).Else(
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NextState("Burst4ReadWaitForTM0"),
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)
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)
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dma_fsm.act("Burst4ReadWaitForTM0",
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master_oe.eq(1), # for start
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start_o_n.eq(1), # start finished, but still need to be driven
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If(sampled_ack, # oups
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fromsbus_req_fifo.re.eq(1), # remove request to avoid infinite repeat
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NextValue(led0, 1),
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NextValue(led1, 1),
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NextState("FinishCycle"),
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).Elif(sampled_tm0,
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Case(ctr, {
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0x0: NextValue(fifo_buffer[ 0: 32], sampled_ad),
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0x1: NextValue(fifo_buffer[32: 64], sampled_ad),
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0x2: NextValue(fifo_buffer[64: 96], sampled_ad),
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#0x3: NextValue(fifo_buffer[96:128], sampled_ad),
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}),
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NextValue(ctr, ctr + 1),
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If(ctr == 0x2, # burst next-to-last
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NextState("Burst4ReadWaitForAck"),
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).Else(
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NextState("Burst4ReadWaitForTM0"),
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)
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)
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)
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dma_fsm.act("Burst4ReadWaitForAck",
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master_oe.eq(1), # for start
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start_o_n.eq(1), # start finished, but still need to be driven
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If(sampled_ack,
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fromsbus_req_fifo.re.eq(1), # remove request
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fromsbus_fifo.we.eq(1),
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fromsbus_fifo_din.blkaddress.eq(fifo_blk_addr),
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fromsbus_fifo_din.data.eq(Cat(fifo_buffer[0:96], sampled_ad)), # we use sampled_ad directly for 96:128
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# fixme: check status ??? (tm0 and tm1 should be active for no-error)
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NextValue(led0, (~sampled_tm0 | ~sampled_tm1)),
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NextState("FinishCycle"),
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)
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)
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dma_fsm.act("Burst4DatCycleTM0",
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master_oe.eq(1), # for start
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ad_oe.eq(1), # for write data
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start_o_n.eq(1), # start finished, but still need to be driven
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Case(ctr, {
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0x0: ad_o_n.eq(~tosbus_fifo_dout.data[ 0: 32]),
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0x1: ad_o_n.eq(~tosbus_fifo_dout.data[32: 64]),
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0x2: ad_o_n.eq(~tosbus_fifo_dout.data[64: 96]),
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#0x3: ad_o_n.eq(~tosbus_fifo_dout.data[96:128]),
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}),
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If(sampled_ack, # oups
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NextValue(led0, 1),
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NextValue(led1, 1),
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tosbus_fifo.re.eq(1), # remove FIFO entry to avoid infinite repeat
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NextState("FinishCycle"),
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).Elif(sampled_tm0,
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NextValue(ctr, ctr + 1),
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If(ctr == 0x2, # burst next-to-last
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NextState("Burst4DatCycleAck"),
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).Else(
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NextState("Burst4DatCycleTM0"),
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)
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)
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)
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dma_fsm.act("Burst4DatCycleAck",
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master_oe.eq(1), # for start
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ad_oe.eq(1), # for write data
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start_o_n.eq(1), # start finished, but still need to be driven
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ad_o_n.eq(~tosbus_fifo_dout.data[96:128]), # last word
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If(sampled_ack,
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tosbus_fifo.re.eq(1), # remove FIFO entry at last
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# fixme: check status ??? (tm0 and tm1 should be active for no-error)
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NextValue(led0, (~sampled_tm0 | ~sampled_tm1)),
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NextState("FinishCycle"),
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)
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)
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@ -37,6 +37,7 @@ import goblin_accel
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# Wishbone stuff
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from sbus_wb import WishboneDomainCrossingMaster
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from sbus_to_fpga_blk_dma import *
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from nubus_mem_wb import NuBus2Wishbone
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from nubus_memfifo_wb import NuBus2WishboneFIFO
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from nubus_cpu_wb import Wishbone2NuBus
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@ -322,12 +323,56 @@ class NuBusFPGA(SoCCore):
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nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
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wishbone_slave_nubus = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus", force_delay=6) # force delay needed to avoid back-to-back transaction running into issue https://github.com/alexforencich/verilog-wishbone/issues/4
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self.submodules.nubus = nubus_full_sampling.NuBus(platform=platform,
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burst_size=4
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data_width = burst_size * 4
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data_width_bits = burst_size * 32
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blk_addr_width = 32 - log2_int(data_width)
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self.tosbus_layout = [
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("address", 32),
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("data", data_width_bits),
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]
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self.fromsbus_layout = [
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("blkaddress", blk_addr_width),
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("data", data_width_bits),
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]
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self.fromsbus_req_layout = [
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("blkaddress", blk_addr_width),
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("dmaaddress", 32),
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]
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self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "nubus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.tosbus_layout), depth=burst_size))
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self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "nubus", "read": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_layout), depth=burst_size))
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self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "nubus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_req_layout), depth=burst_size))
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self.submodules.exchange_with_mem = ExchangeWithMem(soc=self,
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platform=platform,
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tosbus_fifo=self.tosbus_fifo,
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fromsbus_fifo=self.fromsbus_fifo,
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fromsbus_req_fifo=self.fromsbus_req_fifo,
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dram_native_r=self.sdram.crossbar.get_port(mode="read", data_width=data_width_bits),
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dram_native_w=self.sdram.crossbar.get_port(mode="write", data_width=data_width_bits),
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mem_size=avail_sdram//1048576,
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burst_size=burst_size,
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do_checksum = False)
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self.submodules.nubus = nubus_full_sampling.NuBus(soc=self,
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burst_size=burst_size,
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tosbus_fifo=self.tosbus_fifo,
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fromsbus_fifo=self.fromsbus_fifo,
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fromsbus_req_fifo=self.fromsbus_req_fifo,
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wb_read=wishbone_master_sys,
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wb_write=nubus_writemaster_sys,
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wb_dma=wishbone_slave_nubus,
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cd_nubus="nubus")
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#self.submodules.nubus = nubus_full.NuBus(platform=platform,
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#self.submodules.nubus = nubus_full.NuBus(soc=self,
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# burst_size=burst_size,
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# tosbus_fifo=self.tosbus_fifo,
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# fromsbus_fifo=self.fromsbus_fifo,
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# fromsbus_req_fifo=self.fromsbus_req_fifo,
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# wb_read=self.wishbone_master_nubus,
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# wb_write=nubus_writemaster_sys,
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# wb_dma=wishbone_slave_nubus,
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@ -18,7 +18,7 @@ dfii_command_wrdata = 0x10
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dfii_command_rddata = 0x20
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# /!\ keep up to date with csr /!\
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sdram_dfii_base = 0xf0a01000
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sdram_dfii_base = 0xf0a01800
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sdram_dfii_control = sdram_dfii_base + 0x000
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sdram_dfii_pi0_command = sdram_dfii_base + 0x004
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sdram_dfii_pi0_command_issue = sdram_dfii_base + 0x008
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