mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-12-21 04:29:33 +00:00
more stuff thinking about V1.2
This commit is contained in:
Romain Dolbeau
parent
e69b4b946b
commit
cb6e09169e
@ -1,100 +1,100 @@
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set_property IOSTANDARD LVTTL [get_ports {nmrq_n}]
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set_property IOSTANDARD LVTTL [get_ports {start_n}]
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set_property IOSTANDARD LVTTL [get_ports {arb_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_n[0]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[31]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[29]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[27]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[25]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[23]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[21]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[18]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[16]}]
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set_property IOSTANDARD LVTTL [get_ports {nubus_oe}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[17]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[12]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[10]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[8]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[6]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[4]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[5]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[3]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[0]}]
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set_property IOSTANDARD LVTTL [get_ports {tm_n[1]}]
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set_property IOSTANDARD LVTTL [get_ports {tm_n[0]}]
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set_property IOSTANDARD LVTTL [get_ports {reset_n}]
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set_property IOSTANDARD LVTTL [get_ports {rqst_n}]
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set_property IOSTANDARD LVTTL [get_ports {PMOD10}]
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set_property IOSTANDARD LVTTL [get_ports {PMOD11}]
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set_property IOSTANDARD LVTTL [get_ports {PMOD12}]
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set_property IOSTANDARD LVTTL [get_ports {PMOD5}]
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set_property IOSTANDARD LVTTL [get_ports {PMOD6}]
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set_property IOSTANDARD LVTTL [get_ports {PMOD7}]
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set_property IOSTANDARD LVTTL [get_ports {PMOD8}]
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set_property IOSTANDARD LVTTL [get_ports {PMOD9}]
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set_property IOSTANDARD LVTTL [get_ports {RX}]
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set_property IOSTANDARD LVTTL [get_ports {SD_CLK}]
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set_property IOSTANDARD LVTTL [get_ports {SD_CMD}]
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set_property IOSTANDARD LVTTL [get_ports {SD_D0}]
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set_property IOSTANDARD LVTTL [get_ports {SD_D1}]
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set_property IOSTANDARD LVTTL [get_ports {SD_D2}]
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set_property IOSTANDARD LVTTL [get_ports {SD_D3}]
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set_property IOSTANDARD LVTTL [get_ports {TX}]
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set_property IOSTANDARD LVTTL [get_ports {ack_n}]
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set_property IOSTANDARD LVTTL [get_ports {arb_n[3]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_n[1]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[30]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[28]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[26]}]
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set_property IOSTANDARD LVTTL [get_ports {clk_n}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[24]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[22]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[20]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[19]}]
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set_property IOSTANDARD LVTTL [get_ports {ack_o_n}]
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set_property IOSTANDARD LVTTL [get_ports {ack_oe_n}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[0]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[10]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[11]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[12]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[13]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[14]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[15]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[13]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[11]}]
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set_property IOSTANDARD LVTTL [get_ports {clk2x_n}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[9]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[7]}]
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set_property IOSTANDARD LVTTL [get_ports {tm_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[16]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[17]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[18]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[19]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[1]}]
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set_property IOSTANDARD LVTTL [get_ports {usbh0_p}]
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set_property IOSTANDARD LVTTL [get_ports {usbh0_n}]
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set_property IOSTANDARD LVTTL [get_ports {led[8]}]
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set_property IOSTANDARD LVTTL [get_ports {RX}]
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set_property IOSTANDARD LVTTL [get_ports {id_n[1]}]
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set_property IOSTANDARD LVTTL [get_ports {id_n[3]}]
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set_property IOSTANDARD LVTTL [get_ports {id_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[20]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[21]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[22]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[23]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[24]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[25]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[26]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[27]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[28]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[29]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[30]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[31]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[3]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[4]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[5]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[6]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[7]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[8]}]
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set_property IOSTANDARD LVTTL [get_ports {ad_n[9]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_n[0]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_n[1]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_n[3]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_o_n[0]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_o_n[1]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_o_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {arb_o_n[3]}]
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set_property IOSTANDARD LVTTL [get_ports {clk2x_n}]
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set_property IOSTANDARD LVTTL [get_ports {clk_n}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_cec_a}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_clk_n}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_clk_p}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_d0_n}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_d0_p}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_d1_n}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_d1_p}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_d2_n}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_d2_p}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_hpd_a}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_scl_a}]
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set_property IOSTANDARD LVTTL [get_ports {hdmi_sda_a}]
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set_property IOSTANDARD LVTTL [get_ports {id_n[0]}]
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set_property IOSTANDARD LVTTL [get_ports {i2c0_scl}]
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set_property IOSTANDARD LVTTL [get_ports {i2c0_sda}]
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set_property IOSTANDARD LVTTL [get_ports {led[6]}]
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set_property IOSTANDARD LVTTL [get_ports {led[4]}]
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set_property IOSTANDARD LVTTL [get_ports {led[2]}]
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set_property IOSTANDARD LVTTL [get_ports {id_n[1]}]
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set_property IOSTANDARD LVTTL [get_ports {id_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {id_n[3]}]
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set_property IOSTANDARD LVTTL [get_ports {led[0]}]
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set_property IOSTANDARD LVTTL [get_ports {unused0}]
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set_property IOSTANDARD LVTTL [get_ports {vga_clk}]
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set_property IOSTANDARD LVTTL [get_ports {vga_b[7]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_b[6]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_b[5]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_b[4]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_b[3]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_b[2]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_b[1]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_b[0]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_g[7]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_g[6]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_g[4]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_g[5]}]
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set_property IOSTANDARD LVTTL [get_ports {TX}]
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set_property IOSTANDARD LVTTL [get_ports {sd_d2}]
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set_property IOSTANDARD LVTTL [get_ports {sd_d3}]
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set_property IOSTANDARD LVTTL [get_ports {sd_cmd}]
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set_property IOSTANDARD LVTTL [get_ports {sd_clk}]
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set_property IOSTANDARD LVTTL [get_ports {sd_d0}]
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set_property IOSTANDARD LVTTL [get_ports {sd_d1}]
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set_property IOSTANDARD LVTTL [get_ports {led[7]}]
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set_property IOSTANDARD LVTTL [get_ports {led[5]}]
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set_property IOSTANDARD LVTTL [get_ports {led[3]}]
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set_property IOSTANDARD LVTTL [get_ports {led[1]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_hs}]
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set_property IOSTANDARD LVTTL [get_ports {vga_vs}]
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set_property IOSTANDARD LVTTL [get_ports {vga_r[0]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_r[1]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_r[2]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_r[3]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_r[4]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_r[5]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_r[6]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_r[7]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_g[0]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_g[1]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_g[2]}]
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set_property IOSTANDARD LVTTL [get_ports {vga_g[3]}]
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set_property IOSTANDARD LVTTL [get_ports {led[2]}]
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set_property IOSTANDARD LVTTL [get_ports {led[3]}]
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set_property IOSTANDARD LVTTL [get_ports {nmrq_n}]
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set_property IOSTANDARD LVTTL [get_ports {nubus_ad_dir}]
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set_property IOSTANDARD LVTTL [get_ports {nubus_oe}]
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set_property IOSTANDARD LVTTL [get_ports {reset_n}]
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set_property IOSTANDARD LVTTL [get_ports {rqst_n}]
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set_property IOSTANDARD LVTTL [get_ports {rsqt_o_n}]
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set_property IOSTANDARD LVTTL [get_ports {start_n}]
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set_property IOSTANDARD LVTTL [get_ports {start_o_n}]
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set_property IOSTANDARD LVTTL [get_ports {start_oe_n}]
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set_property IOSTANDARD LVTTL [get_ports {tm2_oe_n}]
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set_property IOSTANDARD LVTTL [get_ports {tm_n[0]}]
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set_property IOSTANDARD LVTTL [get_ports {tm_n[1]}]
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set_property IOSTANDARD LVTTL [get_ports {tm_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {tm_n_o[0]}]
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set_property IOSTANDARD LVTTL [get_ports {tm_n_o[1]}]
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set_property IOSTANDARD LVTTL [get_ports {tm_o_n[2]}]
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set_property IOSTANDARD LVTTL [get_ports {tmx_oe_n}]
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set_property IOSTANDARD LVTTL [get_ports {usbh0_n}]
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set_property IOSTANDARD LVTTL [get_ports {usbh0_p}]
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@ -27,12 +27,12 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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#### AB
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# AB TOP LEFT (12)
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set_property PACKAGE_PIN K16 [get_ports {rqst_n}]
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set_property PACKAGE_PIN K15 [get_ports {tm0_n}]
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set_property PACKAGE_PIN J15 [get_ports {start_n}]
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set_property PACKAGE_PIN H15 [get_ports {grant}] # from CPLD
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set_property PACKAGE_PIN J14 [get_ports {fpga_to_cpld_signal}] # to CPLD
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set_property PACKAGE_PIN H17 [get_ports {nubus_master_dir}]
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set_property PACKAGE_PIN G17 [get_ports {reset_n}]
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set_property PACKAGE_PIN K15 [get_ports {start_n}]
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set_property PACKAGE_PIN J15 [get_ports {start_oe_n}]
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set_property PACKAGE_PIN H15 [get_ports {start_o_n}]
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set_property PACKAGE_PIN J14 [get_ports {arb_o_n[0]}]
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set_property PACKAGE_PIN H17 [get_ports {arb_o_n[3]}]
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set_property PACKAGE_PIN G17 [get_ports {nubus_ad_dir}]
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set_property PACKAGE_PIN G18 [get_ports {ad_n[31]}]
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set_property PACKAGE_PIN F18 [get_ports {ad_n[29]}]
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set_property PACKAGE_PIN E18 [get_ports {ad_n[27]}]
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@ -56,12 +56,12 @@ set_property PACKAGE_PIN B11 [get_ports {usbh0_p}]
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# AB TOP RIGHT (12)
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set_property PACKAGE_PIN J18 [get_ports {nmrq_n}]
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set_property PACKAGE_PIN J17 [get_ports {tm1_n}]
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set_property PACKAGE_PIN K13 [get_ports {ack_n}]
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set_property PACKAGE_PIN J13 [get_ports {arb}] # from CPLD
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set_property PACKAGE_PIN H14 [get_ports {fpga_to_cpld_clk}] # to CPLD
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set_property PACKAGE_PIN G14 [get_ports {fpga_to_cpld_signal_2}] # to CPLD
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set_property PACKAGE_PIN G16 [get_ports {nubus_ad_dir}]
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set_property PACKAGE_PIN J17 [get_ports {ack_n}]
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set_property PACKAGE_PIN K13 [get_ports {rsqt_o_n}]
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set_property PACKAGE_PIN J13 [get_ports {ack_oe_n}]
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set_property PACKAGE_PIN H14 [get_ports {ack_o_n}]
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set_property PACKAGE_PIN G14 [get_ports {arb_o_n[2]}]
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set_property PACKAGE_PIN G16 [get_ports {arb_o_n[1]}]
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set_property PACKAGE_PIN H16 [get_ports {clk_n}]
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set_property PACKAGE_PIN F16 [get_ports {ad_n[30]}]
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set_property PACKAGE_PIN F15 [get_ports {ad_n[28]}]
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@ -88,57 +88,57 @@ set_property PACKAGE_PIN A11 [get_ports {usbh0_n}]
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set_property PACKAGE_PIN U9 [get_ports {RX}]
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set_property PACKAGE_PIN U8 [get_ports {id_n[3]}]
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set_property PACKAGE_PIN U7 [get_ports {id_n[0]}]
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set_property PACKAGE_PIN U6 [get_ports {tmoen}] # to CPLD
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set_property PACKAGE_PIN T8 [get_ports {hdmi_hpd_a}]
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set_property PACKAGE_PIN R8 [get_ports {hdmi_sda_a}]
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set_property PACKAGE_PIN R7 [get_ports {hdmi_scl_a}]
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set_property PACKAGE_PIN T6 [get_ports {hdmi_cec_a}]
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set_property PACKAGE_PIN R6 [get_ports {hdmi_clk_p}]
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set_property PACKAGE_PIN R5 [get_ports {hdmi_clk_n}]
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set_property PACKAGE_PIN V2 [get_ports {hdmi_d1_n}]
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set_property PACKAGE_PIN U2 [get_ports {hdmi_d1_p}]
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set_property PACKAGE_PIN K6 [get_ports {vga_clk}]
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set_property PACKAGE_PIN U6 [get_ports {arb_n[3]}]
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set_property PACKAGE_PIN T8 [get_ports {arb_n[0]}]
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set_property PACKAGE_PIN R8 [get_ports {PMOD6}]
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set_property PACKAGE_PIN R7 [get_ports {PMOD5}]
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set_property PACKAGE_PIN T6 [get_ports {PMOD8}]
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set_property PACKAGE_PIN R6 [get_ports {PMOD7}]
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set_property PACKAGE_PIN R5 [get_ports {PMOD10}]
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set_property PACKAGE_PIN V2 [get_ports {PMOD9}]
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set_property PACKAGE_PIN U2 [get_ports {PMOD12}]
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set_property PACKAGE_PIN K6 [get_ports {PMOD11}]
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# CD BOTTOM LEFT (12)
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set_property PACKAGE_PIN N6 [get_ports {vga_b[7]}]
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set_property PACKAGE_PIN M6 [get_ports {vga_b[6]}]
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set_property PACKAGE_PIN L6 [get_ports {vga_b[5]}]
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set_property PACKAGE_PIN L5 [get_ports {vga_b[4]}]
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set_property PACKAGE_PIN N4 [get_ports {vga_b[3]}]
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set_property PACKAGE_PIN M4 [get_ports {vga_b[2]}]
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set_property PACKAGE_PIN M3 [get_ports {vga_b[1]}]
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set_property PACKAGE_PIN M2 [get_ports {vga_b[0]}]
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set_property PACKAGE_PIN K5 [get_ports {vga_g[7]}]
|
||||
set_property PACKAGE_PIN L4 [get_ports {vga_g[6]}]
|
||||
set_property PACKAGE_PIN L3 [get_ports {vga_g[5]}]
|
||||
set_property PACKAGE_PIN K3 [get_ports {vga_g[4]}]
|
||||
set_property PACKAGE_PIN N6 [get_ports {hdmi_hpd_a}]
|
||||
set_property PACKAGE_PIN M6 [get_ports {hdmi_sda_a}]
|
||||
set_property PACKAGE_PIN L6 [get_ports {hdmi_scl_a}]
|
||||
set_property PACKAGE_PIN L5 [get_ports {hdmi_cec_a}]
|
||||
set_property PACKAGE_PIN N4 [get_ports {hdmi_clk_n}]
|
||||
set_property PACKAGE_PIN M4 [get_ports {hdmi_clk_p}]
|
||||
set_property PACKAGE_PIN M3 [get_ports {hdmi_d0_p}]
|
||||
set_property PACKAGE_PIN M2 [get_ports {hdmi_d0_n}]
|
||||
set_property PACKAGE_PIN K5 [get_ports {hdmi_d1_p}]
|
||||
set_property PACKAGE_PIN L4 [get_ports {hdmi_d1_n}]
|
||||
set_property PACKAGE_PIN L3 [get_ports {hdmi_d2_n}]
|
||||
set_property PACKAGE_PIN K3 [get_ports {hdmi_d2_p}]
|
||||
|
||||
# CD TOP RIGHT (13)
|
||||
set_property PACKAGE_PIN V9 [get_ports {TX}]
|
||||
set_property PACKAGE_PIN V7 [get_ports {id_n[2]}]
|
||||
set_property PACKAGE_PIN V6 [get_ports {id_n[1]}]
|
||||
set_property PACKAGE_PIN V5 [get_ports {led[0]}]
|
||||
set_property PACKAGE_PIN V4 [get_ports {led[1]}]
|
||||
set_property PACKAGE_PIN T5 [get_ports {led[2]}]
|
||||
set_property PACKAGE_PIN T4 [get_ports {led[3]}]
|
||||
set_property PACKAGE_PIN U4 [get_ports {vga_hs}]
|
||||
set_property PACKAGE_PIN U3 [get_ports {vga_vs}]
|
||||
set_property PACKAGE_PIN V1 [get_ports {hdmi_d0_n}]
|
||||
set_property PACKAGE_PIN U1 [get_ports {hdmi_d0_p}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {hdmi_d2_n}]
|
||||
set_property PACKAGE_PIN R3 [get_ports {hdmi_d2_p}]
|
||||
set_property PACKAGE_PIN V5 [get_ports {arb_n[2]}]
|
||||
set_property PACKAGE_PIN V4 [get_ports {arb_n[1]}]
|
||||
set_property PACKAGE_PIN T5 [get_ports {clk2x_n}]
|
||||
set_property PACKAGE_PIN T4 [get_ports {SD_D1}]
|
||||
set_property PACKAGE_PIN U4 [get_ports {SD_D0}]
|
||||
set_property PACKAGE_PIN U3 [get_ports {SD_CLK}]
|
||||
set_property PACKAGE_PIN V1 [get_ports {SD_CMD}]
|
||||
set_property PACKAGE_PIN U1 [get_ports {SD_D3}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {SD_D2}]
|
||||
set_property PACKAGE_PIN R3 [get_ports {tmx_oe_n}]
|
||||
|
||||
# CD BOTTOM RIGHT (12)
|
||||
set_property PACKAGE_PIN P5 [get_ports {vga_r[0]}]
|
||||
set_property PACKAGE_PIN N5 [get_ports {vga_r[1]}]
|
||||
set_property PACKAGE_PIN P4 [get_ports {vga_r[2]}]
|
||||
set_property PACKAGE_PIN P3 [get_ports {vga_r[3]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {vga_r[4]}]
|
||||
set_property PACKAGE_PIN R1 [get_ports {vga_r[5]}]
|
||||
set_property PACKAGE_PIN R2 [get_ports {vga_r[6]}]
|
||||
set_property PACKAGE_PIN P2 [get_ports {vga_r[7]}]
|
||||
set_property PACKAGE_PIN N2 [get_ports {vga_g[0]}]
|
||||
set_property PACKAGE_PIN N1 [get_ports {vga_g[1]}]
|
||||
set_property PACKAGE_PIN M1 [get_ports {vga_g[2]}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {vga_g[3]}]
|
||||
set_property PACKAGE_PIN P5 [get_ports {tm_n[0]}]
|
||||
set_property PACKAGE_PIN N5 [get_ports {tm_n[1]}]
|
||||
set_property PACKAGE_PIN P4 [get_ports {tm_n_o[1]}]
|
||||
set_property PACKAGE_PIN P3 [get_ports {tm_n_o[0]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {tm2_oe_n}]
|
||||
set_property PACKAGE_PIN R1 [get_ports {tm_o_n[2]}]
|
||||
set_property PACKAGE_PIN R2 [get_ports {tm_n[2]}]
|
||||
set_property PACKAGE_PIN P2 [get_ports {reset_n}]
|
||||
set_property PACKAGE_PIN N2 [get_ports {led[0]}]
|
||||
set_property PACKAGE_PIN N1 [get_ports {led[1]}]
|
||||
set_property PACKAGE_PIN M1 [get_ports {led[2]}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {led[3]}]
|
||||
|
||||
|
||||
475
nubus-to-ztex-gateware/slave_V1.2_tb.sv
Normal file
475
nubus-to-ztex-gateware/slave_V1.2_tb.sv
Normal file
@ -0,0 +1,475 @@
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module nubus_slave_tb ();
|
||||
|
||||
`include "nubus_tb.svh"
|
||||
|
||||
parameter TEST_CARD_ID = 'hc;
|
||||
parameter TEST_ADDR = 'hFc000000;
|
||||
parameter TEST_DATA = 'h87654321;
|
||||
parameter [1:0] MEMORY_WAIT_CLOCKS = 1;
|
||||
parameter DEBUG_NUBUS_START = 0;
|
||||
parameter ROM_ADDR = 'hFcFFF000;
|
||||
parameter PING_ADDR = 'hFcB00000;
|
||||
|
||||
// Clock (rising is driving edge, faling is sampling)
|
||||
tri1 bd_clk48;
|
||||
|
||||
// Slot Identification
|
||||
tri1 [3:0] nub_idn;
|
||||
// Clock (rising is driving edge, faling is sampling)
|
||||
tri1 nub_clkn;
|
||||
// Clock 90 (rising is driving edge, faling is sampling)
|
||||
tri1 nub_clk2xn;
|
||||
// Reset [Open Collector]
|
||||
tri1 nub_resetn;
|
||||
// Power Fail Warning [Control]
|
||||
//tri1 nub_pfwn;
|
||||
// Address/Data [Address/Data]
|
||||
tri1 [31:0] nub_adn;
|
||||
// Transfer Mode [Control]
|
||||
tri1 nub_tm0n;
|
||||
tri1 nub_tm1n;
|
||||
tri1 nub_tm2n;
|
||||
// Start [Control]
|
||||
tri1 nub_startn;
|
||||
// Request [Open Collector]
|
||||
tri1 nub_rqstn;
|
||||
// Acknowledge [Control]
|
||||
tri1 nub_ackn;
|
||||
// Arbitration [Open Collector]
|
||||
tri1 [3:0] nub_arbn;
|
||||
// Non-Master Request [Open Collector]
|
||||
tri1 nub_nmrqn;
|
||||
// System Parity [Address/Data]
|
||||
//tri1 nub_spn;
|
||||
// System Parity Valid [Address/Data]
|
||||
//tri1 nub_spvn;
|
||||
|
||||
tri1 [1:0] leds;
|
||||
|
||||
tri unused0, tmoen, unused1, unused2;
|
||||
tri arbcy_n;
|
||||
tri grant;
|
||||
tri nubus_oe, nubus_ad_dir;
|
||||
tri reset_n_3v3, clk_n_3v3, tm0_n_3v3, tm1_n_3v3, start_n_3v3, ack_n_3v3, rqst_n_3v3;
|
||||
tri [3:0] id_n_3v3;
|
||||
tri [31:0] ad_n_3v3;
|
||||
tri [3:0] arb_o_n;
|
||||
tri tm0_o_n, tm1_o_n, tmx_oe_n;
|
||||
tri start_o_n, start_oe_n;
|
||||
tri ack_o_n, ack_oe_n;
|
||||
tri rqst_o_n;
|
||||
|
||||
|
||||
tri clk2x_n_3v3;
|
||||
tri tm2_n_3v3, tm2_o_n, tm2_oe_n;
|
||||
|
||||
|
||||
|
||||
assign nub_idn = ~ TEST_CARD_ID;
|
||||
//assign nub_arbn = 'b1111;
|
||||
|
||||
// actually 74lvt245, same digital function
|
||||
sn74fct245 shifters_b0(.data_5v(nub_adn[ 7: 0]),
|
||||
.data_3v3(ad_n_3v3[ 7: 0]),
|
||||
.nubus_oe(nubus_oe),
|
||||
.nubus_ad_dir(nubus_ad_dir));
|
||||
sn74fct245 shifters_b1(.data_5v(nub_adn[15: 8]),
|
||||
.data_3v3(ad_n_3v3[15: 8]),
|
||||
.nubus_oe(nubus_oe),
|
||||
.nubus_ad_dir(nubus_ad_dir));
|
||||
sn74fct245 shifters_b2(.data_5v(nub_adn[23:16]),
|
||||
.data_3v3(ad_n_3v3[23:16]),
|
||||
.nubus_oe(nubus_oe),
|
||||
.nubus_ad_dir(nubus_ad_dir));
|
||||
sn74fct245 shifters_b3(.data_5v(nub_adn[31:24]),
|
||||
.data_3v3(ad_n_3v3[31:24]),
|
||||
.nubus_oe(nubus_oe),
|
||||
.nubus_ad_dir(nubus_ad_dir));
|
||||
|
||||
tri1 nmrq_3v3_n;
|
||||
|
||||
|
||||
sn74lvt145_quarter driver_u1a(.oe_n(nmrq_3v3_n),
|
||||
.in(0),
|
||||
.out(nub_nmrqn));
|
||||
sn74lvt145_quarter driver_u1b(.oe_n(rqst_o_n),
|
||||
.in(0),
|
||||
.out(nub_rqstn));
|
||||
sn74lvt145_quarter driver_u1c(.oe_n(start_oe_n),
|
||||
.in(start_o_n),
|
||||
.out(nub_startn));
|
||||
sn74lvt145_quarter driver_u1d(.oe_n(ack_oe_n),
|
||||
.in(ack_o_n),
|
||||
.out(nub_ackn));
|
||||
|
||||
sn74lvt145_quarter driver_u3a(.oe_n(arb_o_n[0]),
|
||||
.in(0),
|
||||
.out(nub_arbn[0]));
|
||||
sn74lvt145_quarter driver_u3b(.oe_n(arb_o_n[1]),
|
||||
.in(0),
|
||||
.out(nub_arbn[1]));
|
||||
sn74lvt145_quarter driver_u3c(.oe_n(arb_o_n[3]),
|
||||
.in(0),
|
||||
.out(nub_arbn[3]));
|
||||
sn74lvt145_quarter driver_u3d(.oe_n(arb_o_n[2]),
|
||||
.in(0),
|
||||
.out(nub_arbn[2]));
|
||||
|
||||
sn74lvt145_quarter driver_u2a(.oe_n(tmx_oe_n),
|
||||
.in(tm1_o_n),
|
||||
.out(nub_tm1n));
|
||||
sn74lvt145_quarter driver_u2b(.oe_n(tmx_oe_n),
|
||||
.in(tm0_o_n),
|
||||
.out(nub_tm0n));
|
||||
sn74lvt145_quarter driver_u2c(.oe_n(tm2_oe_n),
|
||||
.in(tm2_o_n),
|
||||
.out(nub_tm2n));
|
||||
|
||||
sn74cb3t3125 shifters_u4(.oe_n('h0),
|
||||
.A({start_n_3v3, ack_n_3v3, clk_n_3v3, rqst_n_3v3 }),
|
||||
.B({nub_startn, nub_ackn, nub_clkn, nub_rqstn }));
|
||||
sn74cb3t3125 shifters_u13(.oe_n('h0),
|
||||
.A({reset_n_3v3, tm2_n_3v3, tm0_n_3v3, tm1_n_3v3}),
|
||||
.B({nub_resetn, nub_tm2n, nub_tm0n, nub_tm1n }));
|
||||
|
||||
assign clk2x_n_3v3 = nub_clk2n;
|
||||
|
||||
ztex213_nubus_V1_2 UNuBus (
|
||||
// NuBus lines only
|
||||
.clk48(bd_clk48),
|
||||
.clk_3v3_n(clk_n_3v3),
|
||||
.reset_3v3_n(reset_n_3v3),
|
||||
.nubus_clk2x_n(clk2x_n_3v3),
|
||||
.user_led0(leds[0]),
|
||||
.user_led1(leds[1]),
|
||||
.user_led2(leds[2]),
|
||||
.user_led3(leds[3]),
|
||||
.nubus_tm2_n(tm2_n_3v3),
|
||||
.id_3v3_n(id_n_3v3),
|
||||
.ad_3v3_n(ad_n_3v3),
|
||||
.tm0_3v3_n(tm0_n_3v3),
|
||||
.tm1_3v3_n(tm1_n_3v3),
|
||||
.tm0_o_n(tm0_o_n),
|
||||
.tm1_o_n(tm1_o_n),
|
||||
.tmx_oe_n(tmx_oe_n),
|
||||
.start_3v3_n(start_n_3v3),
|
||||
.start_o_n(start_o_n),
|
||||
.start_oe_n(start_oe_n),
|
||||
.rqst_3v3_n(rqst_n_3v3),
|
||||
.rqst_o_n(rqst_o_n),
|
||||
.nmrq_3v3_n(nmrq_n_3v3), // output only, direct to driver
|
||||
.ack_3v3_n(ack_n_3v3),
|
||||
.ack_o_n(ack_o_n),
|
||||
.ack_oe_n(ack_oe_n),
|
||||
.arb_n_3v3(arb_n_3v3),
|
||||
.arb_o_n(arb_o_n),
|
||||
.nubus_ad_dir(nubus_ad_dir),
|
||||
.nubus_oe(nubus_oe),
|
||||
.clk2x_3v3_n(clk2x_n_3v3),
|
||||
.tm2_3v3_n(tm2_n_3v3),
|
||||
.tm2_o_n(tm2_o_n),
|
||||
.tm2_oe_n(tm2_oe_n)
|
||||
);
|
||||
|
||||
|
||||
// State machine of test bench
|
||||
reg tst_clkn;
|
||||
reg tst_clk2xn;
|
||||
reg tst_clk48;
|
||||
reg tst_resetn;
|
||||
reg tst_startn;
|
||||
reg tst_ackn; // half clkn delayed ackn
|
||||
reg [1:0] tst_tmn;
|
||||
reg [1:0] tst_statusn;
|
||||
reg [31:0] tst_addrn;
|
||||
reg [31:0] tst_wdatan;
|
||||
reg [31:0] tst_rdatan;
|
||||
reg tst_rqstn;
|
||||
|
||||
reg mastermode_start;
|
||||
reg mastermode_tmack;
|
||||
|
||||
assign nub_clkn = tst_clkn;
|
||||
assign nub_clk2xn = tst_clk2xn;
|
||||
assign bd_clk48 = tst_clk48;
|
||||
assign nub_resetn = tst_resetn;
|
||||
assign nub_rqstn = tst_rqstn;
|
||||
// Drive NuBus signals
|
||||
assign nub_startn = mastermode_start ? 'bZ: tst_startn;
|
||||
assign nub_tm0n = (tst_startn & ~mastermode_tmack) ? 'bZ : tst_tmn[0];
|
||||
assign nub_tm1n = (tst_startn & ~mastermode_tmack) ? 'bZ : tst_tmn[1];
|
||||
assign nub_ackn = (tst_startn & ~mastermode_tmack) ? 'bZ : tst_ackn;
|
||||
|
||||
// Drive NuBus address/data lines
|
||||
wire [31:0] tst_adn = tst_startn ? tst_wdatan : tst_addrn;
|
||||
wire tst_nuboen = (tst_startn & tst_tmn[1]) | mastermode_start;
|
||||
assign nub_adn = tst_nuboen ? 'bZ : tst_adn;
|
||||
|
||||
// Inverted verions of registers
|
||||
wire [31:0] tst_rdata = ~tst_rdatan;
|
||||
wire [31:0] tst_addr = ~tst_addrn;
|
||||
|
||||
initial begin
|
||||
$display ("Start virtual master (vm) writes and reads to/from NuBus slave memory module");
|
||||
$dumpfile("nubus_slave_tb.vcd");
|
||||
$dumpvars;
|
||||
#1;
|
||||
|
||||
mastermode_start <= 0;
|
||||
mastermode_tmack <= 0;
|
||||
|
||||
tst_clkn <= 1;
|
||||
tst_resetn <= 0;
|
||||
tst_rqstn <= 'bz;
|
||||
tst_addrn <= 'hFFFFFFFF;
|
||||
tst_wdatan <= 'hFFFFFFFF;
|
||||
tst_rdatan <= 'hFFFFFFFF;
|
||||
tst_startn <= 1;
|
||||
tst_statusn<= TMN_TRY_AGAIN_LATER;
|
||||
tst_tmn <= TMN_NOP;
|
||||
|
||||
@ (posedge nub_clkn);
|
||||
@ (posedge nub_clkn);
|
||||
tst_resetn <= 1;
|
||||
|
||||
#2000;
|
||||
|
||||
@ (posedge nub_clkn);
|
||||
$display ("%g: %b", $time, nub_startn);
|
||||
|
||||
$display ("WORD ---------------------------");
|
||||
write_word(TMADN_WR_WORD, TEST_ADDR+0, TEST_DATA);
|
||||
read_word (TMADN_RD_WORD, TEST_ADDR+0);
|
||||
check_word(TMADN_RD_WORD, TEST_DATA);
|
||||
$display ("HALF 0 -------------------------");
|
||||
write_word(TMADN_WR_HALF_0, TEST_ADDR+4, TEST_DATA);
|
||||
read_word (TMADN_RD_HALF_0, TEST_ADDR+4);
|
||||
check_word(TMADN_RD_HALF_0, TEST_DATA);
|
||||
$display ("HALF 1 -------------------------");
|
||||
write_word(TMADN_WR_HALF_1, TEST_ADDR+8, TEST_DATA);
|
||||
read_word (TMADN_RD_HALF_1, TEST_ADDR+8);
|
||||
check_word(TMADN_RD_HALF_1, TEST_DATA);
|
||||
|
||||
$display ("BYTE 0 -------------------------");
|
||||
write_word(TMADN_WR_BYTE_0, TEST_ADDR+12, TEST_DATA);
|
||||
read_word (TMADN_RD_BYTE_0, TEST_ADDR+12);
|
||||
check_word(TMADN_RD_BYTE_0, TEST_DATA);
|
||||
$display ("BYTE 1 -------------------------");
|
||||
write_word(TMADN_WR_BYTE_1, TEST_ADDR+16, TEST_DATA);
|
||||
read_word (TMADN_RD_BYTE_1, TEST_ADDR+16);
|
||||
check_word(TMADN_RD_BYTE_1, TEST_DATA);
|
||||
$display ("BYTE 2 -------------------------");
|
||||
write_word(TMADN_WR_BYTE_2, TEST_ADDR+20, TEST_DATA);
|
||||
read_word (TMADN_RD_BYTE_2, TEST_ADDR+20);
|
||||
check_word(TMADN_RD_BYTE_2, TEST_DATA);
|
||||
$display ("BYTE 3 -------------------------");
|
||||
write_word(TMADN_WR_BYTE_3, TEST_ADDR+24, TEST_DATA);
|
||||
read_word (TMADN_RD_BYTE_3, TEST_ADDR+24);
|
||||
check_word(TMADN_RD_BYTE_3, TEST_DATA);
|
||||
|
||||
// $display ("BLOCK2 -------------------------");
|
||||
// read_block2 (TMADN_RD_BLOCK, TEST_ADDR);
|
||||
|
||||
#500
|
||||
|
||||
// Check Rom
|
||||
$display ("ROM ---------------------------");
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4092);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4088);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4084);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4080);
|
||||
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+0);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+8);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+12);
|
||||
|
||||
#1000;
|
||||
|
||||
// check PingMaster
|
||||
$display ("PING ---------------------------");
|
||||
write_word(TMADN_WR_WORD, PING_ADDR+0, 'h00C0FFEE);
|
||||
read_word (TMADN_RD_WORD, PING_ADDR+0);
|
||||
write_word(TMADN_WR_WORD, PING_ADDR+4, 'h00096240);
|
||||
//read_word (TMADN_RD_WORD, ROM_ADDR+0);
|
||||
|
||||
mastermode_start <= 1;
|
||||
mastermode_tmack <= 0;
|
||||
tst_ackn <= 1;
|
||||
|
||||
@ (negedge nub_startn);
|
||||
#1
|
||||
$display ("GOT START ---------------------------");
|
||||
$display ("%g (received ) address: $%h", $time, ~nub_adn);
|
||||
@ (negedge nub_clkn);
|
||||
#1
|
||||
@ (negedge nub_clkn);
|
||||
#1
|
||||
@ (negedge nub_clkn);
|
||||
#1
|
||||
$display ("%g (received ) data: $%h", $time, ~nub_adn);
|
||||
@ (posedge nub_clkn);
|
||||
mastermode_tmack <= 1;
|
||||
tst_ackn <= 0;
|
||||
tst_tmn <= TMN_COMPLETE;
|
||||
|
||||
@ (posedge nub_clkn);
|
||||
mastermode_start <= 0;
|
||||
mastermode_tmack <= 0;
|
||||
|
||||
#2000;
|
||||
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// ======================================================
|
||||
// Write task
|
||||
// ======================================================
|
||||
|
||||
task write_word;
|
||||
input [3:0] tmadn;
|
||||
input [31:0] addr;
|
||||
input [31:0] data;
|
||||
begin
|
||||
@ (posedge nub_clkn);
|
||||
tst_wdatan <= ~data;
|
||||
tst_addrn[31:2] <= ~addr[31:2];
|
||||
tst_addrn[ 1:0] <= tmadn[1:0];
|
||||
tst_tmn <= tmadn[3:2];
|
||||
tst_startn <= 0;
|
||||
tst_ackn <= 1;
|
||||
//tst_statusn <= TMN_TRY_AGAIN_LATER;
|
||||
@ (posedge nub_clkn);
|
||||
tst_startn <= 1;
|
||||
tst_ackn <= nub_ackn;
|
||||
do begin
|
||||
@ (negedge nub_clkn);
|
||||
tst_ackn <= nub_ackn;
|
||||
tst_statusn <= { nub_tm1n, nub_tm0n };
|
||||
//@ (posedge nub_clkn);
|
||||
end while (tst_ackn) ;
|
||||
$display ("%g (write) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, data, get_status_str(tst_statusn));
|
||||
end
|
||||
endtask
|
||||
|
||||
// ======================================================
|
||||
// Read task
|
||||
// ======================================================
|
||||
|
||||
task read_word;
|
||||
input [3:0] tmadn;
|
||||
input [31:0] addr;
|
||||
begin
|
||||
@ (posedge nub_clkn);
|
||||
tst_tmn <= tmadn[3:2];
|
||||
tst_addrn[ 1:0] <= tmadn[1:0];
|
||||
tst_addrn[31:2] <= ~addr[31:2];
|
||||
tst_startn <= 0;
|
||||
tst_ackn <= 1;
|
||||
//tst_statusn <= TMN_TRY_AGAIN_LATER;
|
||||
@ (posedge nub_clkn);
|
||||
tst_startn <= 1;
|
||||
tst_ackn <= nub_ackn;
|
||||
do begin
|
||||
@ (negedge nub_clkn);
|
||||
tst_rdatan <= nub_adn;
|
||||
tst_ackn <= nub_ackn;
|
||||
tst_statusn <= { nub_tm1n, nub_tm0n };
|
||||
//@ (posedge nub_clkn);
|
||||
end while (tst_ackn) ;
|
||||
$display ("%g (read ) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
|
||||
end
|
||||
endtask
|
||||
|
||||
// ======================================================
|
||||
// Verify data writen to memory with read from
|
||||
// asume memory befor write was $00000000
|
||||
// ======================================================
|
||||
|
||||
task check_word
|
||||
(
|
||||
input [3:0] tm,
|
||||
input [31:0] data_wr
|
||||
);
|
||||
reg [31:0] expected;
|
||||
begin
|
||||
expected = (data_wr & get_mask(tm));
|
||||
if (tst_rdata == expected)
|
||||
$display (":) PASSED");
|
||||
else
|
||||
$display (":( FAILED expected: $%h found: $%h", expected, tst_rdata);
|
||||
$display(" ");
|
||||
end
|
||||
endtask // verify
|
||||
|
||||
// ======================================================
|
||||
// Read block2 task
|
||||
// Currently unsupported (introduced with Q700/Q900, not in the NTC)
|
||||
// ======================================================
|
||||
|
||||
task read_block2;
|
||||
input [3:0] tmadn;
|
||||
input [31:0] addr;
|
||||
begin
|
||||
@ (posedge nub_clkn);
|
||||
tst_tmn <= tmadn[3:2];
|
||||
tst_addrn[ 1:0] <= tmadn[1:0];
|
||||
tst_addrn[ 2:2] <= 1; // this indicates size 2
|
||||
tst_addrn[31:3] <= ~addr[31:3];
|
||||
tst_startn <= 0;
|
||||
//tst_statusn <= TMN_TRY_AGAIN_LATER;
|
||||
@ (posedge nub_clkn);
|
||||
tst_startn <= 1;
|
||||
tst_ackn <= nub_ackn;
|
||||
do begin
|
||||
@ (negedge nub_clkn);
|
||||
tst_rdatan <= nub_adn;
|
||||
tst_ackn <= nub_ackn;
|
||||
tst_statusn <= { nub_tm1n, nub_tm0n };
|
||||
//@ (posedge nub_clkn);
|
||||
end while (tst_statusn[0]) ;
|
||||
$display ("%g (block0/2) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
|
||||
do begin
|
||||
@ (negedge nub_clkn);
|
||||
tst_rdatan <= nub_adn;
|
||||
tst_ackn <= nub_ackn;
|
||||
tst_statusn <= { nub_tm1n, nub_tm0n };
|
||||
//@ (posedge nub_clkn);
|
||||
end while (tst_ackn) ;
|
||||
$display ("%g (block1/2) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
|
||||
end
|
||||
endtask // read block2
|
||||
|
||||
// ======================================================
|
||||
// Clock generators
|
||||
// ======================================================
|
||||
|
||||
always begin
|
||||
tst_clkn <= 1;
|
||||
#75.075;
|
||||
tst_clkn <= 0;
|
||||
if (DEBUG_NUBUS_START) begin
|
||||
if (~nub_startn)
|
||||
$display ("%g (NuBus Start) /ad: $%h {/tmadn}: %b%b%b%b", $time, nub_adn, nub_tm1n, nub_tm0n, nub_adn[1], nub_adn[0]);
|
||||
end
|
||||
#25.025;
|
||||
end
|
||||
always begin
|
||||
tst_clk2xn <= 0;
|
||||
#25.025;
|
||||
tst_clk2xn <= 1;
|
||||
#25.025;
|
||||
end
|
||||
|
||||
always begin
|
||||
tst_clk48 <= 0;
|
||||
#10.41666666;
|
||||
tst_clk48 <= 1;
|
||||
#10.41666666;
|
||||
end
|
||||
|
||||
endmodule
|
||||
37
nubus-to-ztex-gateware/sn74cb3t3125.v
Normal file
37
nubus-to-ztex-gateware/sn74cb3t3125.v
Normal file
@ -0,0 +1,37 @@
|
||||
module sn74cb3t3125
|
||||
(
|
||||
input [3:0] oe_n,
|
||||
inout [3:0] A,
|
||||
input [3:0] B
|
||||
);
|
||||
|
||||
wire [3:0] tA;
|
||||
wire [3:0] tB;
|
||||
|
||||
/*
|
||||
assign A[0] = oe_n[0] ? 'bZ : tA[0];
|
||||
assign A[1] = oe_n[1] ? 'bZ : tA[1];
|
||||
assign A[2] = oe_n[2] ? 'bZ : tA[2];
|
||||
assign A[3] = oe_n[3] ? 'bZ : tA[3];
|
||||
assign B[0] = oe_n[0] ? 'bZ : tB[0];
|
||||
assign B[1] = oe_n[1] ? 'bZ : tB[1];
|
||||
assign B[2] = oe_n[2] ? 'bZ : tB[2];
|
||||
assign B[3] = oe_n[3] ? 'bZ : tB[3];
|
||||
|
||||
assign tA[0] = A[0] === 'bZ ? B[0] : 'bZ;
|
||||
assign tA[1] = A[1] === 'bZ ? B[1] : 'bZ;
|
||||
assign tA[2] = A[2] === 'bZ ? B[2] : 'bZ;
|
||||
assign tA[3] = A[3] === 'bZ ? B[3] : 'bZ;
|
||||
assign tB[0] = B[0] === 'bZ ? A[0] : 'bZ;
|
||||
assign tB[1] = B[1] === 'bZ ? A[1] : 'bZ;
|
||||
assign tB[2] = B[2] === 'bZ ? A[2] : 'bZ;
|
||||
assign tB[3] = B[3] === 'bZ ? A[3] : 'bZ;
|
||||
*/
|
||||
|
||||
assign A[0] = oe_n[0] ? 'bZ : B[0];
|
||||
assign A[1] = oe_n[1] ? 'bZ : B[1];
|
||||
assign A[3] = oe_n[2] ? 'bZ : B[2];
|
||||
assign A[3] = oe_n[3] ? 'bZ : B[3];
|
||||
|
||||
|
||||
endmodule // sn74cb3t3125
|
||||
@ -56,6 +56,7 @@ _io = [
|
||||
|
||||
# NuBusFPGA I/O
|
||||
|
||||
# I/O
|
||||
_nubus_io_v1_0 = [
|
||||
## leds on the NuBus board
|
||||
("user_led", 0, Pins("V5"), IOStandard("lvcmos33")), #LED0
|
||||
@ -99,6 +100,42 @@ _nubus_io_v1_0 = [
|
||||
),
|
||||
]
|
||||
|
||||
_nubus_io_v1_2 = [
|
||||
## leds on the NuBus board
|
||||
("user_led", 0, Pins("N2"), IOStandard("lvcmos33")), #LED0
|
||||
("user_led", 1, Pins("N1"), IOStandard("lvcmos33")), #LED1
|
||||
("user_led", 2, Pins("M1"), IOStandard("lvcmos33")), #LED2
|
||||
("user_led", 3, Pins("L1"), IOStandard("lvcmos33")), #LED3
|
||||
## serial header for console
|
||||
("serial", 0,
|
||||
Subsignal("tx", Pins("V9")), # FIXME: might be the other way round
|
||||
Subsignal("rx", Pins("U9")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
## USB
|
||||
("usb", 0,
|
||||
Subsignal("dp", Pins("B11")),
|
||||
Subsignal("dm", Pins("A11")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
## HDMI
|
||||
("hdmi", 0,
|
||||
Subsignal("clk_p", Pins("M4"), IOStandard("TMDS_33")),
|
||||
Subsignal("clk_n", Pins("N4"), IOStandard("TMDS_33")),
|
||||
Subsignal("data0_p", Pins("M3"), IOStandard("TMDS_33")),
|
||||
Subsignal("data0_n", Pins("M2"), IOStandard("TMDS_33")),
|
||||
Subsignal("data1_p", Pins("K5"), IOStandard("TMDS_33")),
|
||||
Subsignal("data1_n", Pins("L4"), IOStandard("TMDS_33")),
|
||||
Subsignal("data2_p", Pins("K3"), IOStandard("TMDS_33")),
|
||||
Subsignal("data2_n", Pins("L3"), IOStandard("TMDS_33")),
|
||||
Subsignal("hpd", Pins("N6"), IOStandard("LVCMOS33")),
|
||||
Subsignal("sda", Pins("M6"), IOStandard("LVCMOS33")),
|
||||
Subsignal("scl", Pins("L6"), IOStandard("LVCMOS33")),
|
||||
Subsignal("cec", Pins("L5"), IOStandard("LVCMOS33")),
|
||||
),
|
||||
]
|
||||
|
||||
# NuBus
|
||||
_nubus_nubus_v1_0 = [
|
||||
("clk_3v3_n", 0, Pins("H16"), IOStandard("lvttl")),
|
||||
("clk2x_3v3_n", 0, Pins("T5"), IOStandard("lvttl")),
|
||||
@ -128,6 +165,39 @@ _nubus_nubus_v1_0 = [
|
||||
("fpga_to_cpld_signal_2",0, Pins("G14"), IOStandard("lvttl")),
|
||||
]
|
||||
|
||||
_nubus_nubus_v1_2 = [
|
||||
("clk_3v3_n", 0, Pins("H16"), IOStandard("lvttl")),
|
||||
("clk2x_3v3_n", 0, Pins("T5"), IOStandard("lvttl")),
|
||||
("ack_3v3_n", 0, Pins("J17"), IOStandard("lvttl")),
|
||||
("ack_o_n", 0, Pins("H14"), IOStandard("lvttl")),
|
||||
("ack_oe_n", 0, Pins("J13"), IOStandard("lvttl")),
|
||||
("nmrq_3v3_n", 0, Pins("J18"), IOStandard("lvttl")),
|
||||
("reset_3v3_n", 0, Pins("P2"), IOStandard("lvttl")),
|
||||
("rqst_3v3_n" , 0, Pins("K16"), IOStandard("lvttl")),
|
||||
("rqst_o_n" , 0, Pins("K13"), IOStandard("lvttl")),
|
||||
("start_3v3_n", 0, Pins("K15"), IOStandard("lvttl")),
|
||||
("start_o_n", 0, Pins("H15"), IOStandard("lvttl")),
|
||||
("start_oe_n", 0, Pins("J15"), IOStandard("lvttl")),
|
||||
("ad_3v3_n", 0, Pins("A13 A14 C12 B12 B13 B14 A15 A16 "
|
||||
"D12 D13 D14 C14 B16 B17 D15 C15 "
|
||||
"B18 A18 C16 C17 E15 E16 F14 F13 "
|
||||
"D17 D18 E17 E18 F15 F18 F16 G18 "), IOStandard("lvttl")),
|
||||
("arb_3v3_n", 0, Pins("T8 V4 V5 U6"), IOStandard("lvttl")),
|
||||
("arb_o_n", 0, Pins("J14 G16 G14 H17"), IOStandard("lvttl")),
|
||||
("id_3v3_n", 0, Pins("U7 V6 V7 U8"), IOStandard("lvttl")),
|
||||
("tm0_3v3_n", 0, Pins("P5"), IOStandard("lvttl")),
|
||||
("tm0_o_n", 0, Pins("P3"), IOStandard("lvttl")),
|
||||
("tm1_3v3_n", 0, Pins("N5"), IOStandard("lvttl")),
|
||||
("tm1_o_n", 0, Pins("P4"), IOStandard("lvttl")),
|
||||
("tmx_oe_n", 0, Pins("R3"), IOStandard("lvttl")),
|
||||
("tm2_3v3_n", 0, Pins("R2"), IOStandard("lvttl")),
|
||||
("tm2_o_n", 0, Pins("R1"), IOStandard("lvttl")),
|
||||
("tm2_oe_n", 0, Pins("T1"), IOStandard("lvttl")),
|
||||
|
||||
("nubus_oe", 0, Pins("G13"), IOStandard("lvttl")),
|
||||
("nubus_ad_dir", 0, Pins("G17"), IOStandard("lvttl"))),
|
||||
]
|
||||
|
||||
# Connectors ---------------------------------------------------------------------------------------
|
||||
connectors = [
|
||||
]
|
||||
@ -148,9 +218,11 @@ class Platform(XilinxPlatform):
|
||||
}[variant]
|
||||
nubus_io = {
|
||||
"V1.0" : _nubus_io_v1_0,
|
||||
"V1.2" : _nubus_io_v1_2,
|
||||
}[version]
|
||||
nubus_nubus = {
|
||||
"V1.0" : _nubus_nubus_v1_0,
|
||||
"V1.2" : _nubus_nubus_v1_2,
|
||||
}[version]
|
||||
self.speedgrade = -1
|
||||
if (device[-1] == '2'):
|
||||
|
||||
@ -0,0 +1,109 @@
|
||||
(module RJ45_UDE_RB1-125B8G1A (layer F.Cu) (tedit 5F6F3CF6)
|
||||
(descr "1 Port RJ45 Connector Through Hole 10/100/1000 Base-T, https://datasheet.lcsc.com/szlcsc/1901091107_UDE-Corp-RB1-125B8G1A_C363353.pdf#page=3")
|
||||
(tags "RJ45 ethernet")
|
||||
(fp_text reference REF** (at 6 -3.5) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value RJ45_UDE_RB1-125B8G1A (at 5.5 21) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -0.6 -2) (end -2.16 -2) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 -1.4) (end 0.6 -2) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 -1.4) (end -0.6 -2) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 10.83 9.09) (end 12.03 9.09) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 12.03 9.09) (end 12.03 3.69) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 12.03 3.69) (end 10.83 3.69) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 10.83 3.69) (end 10.83 9.09) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 10.83 9.09) (end 12.03 7.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 10.83 8.09) (end 12.03 6.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 10.83 7.09) (end 12.03 5.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 10.83 6.09) (end 12.03 4.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 10.83 5.09) (end 12.03 3.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 10.83 4.09) (end 11.23 3.69) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.6 6.09) (end 0.6 4.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.6 9.09) (end 0.6 9.09) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 0.6 9.09) (end 0.6 3.69) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.6 9.09) (end 0.6 7.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.6 8.09) (end 0.6 6.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.6 3.69) (end -0.6 9.09) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.6 5.09) (end 0.6 3.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.6 7.09) (end 0.6 5.89) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.6 4.09) (end -0.2 3.69) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 0.6 3.69) (end -0.6 3.69) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 13.59 -2) (end 13.59 19.78) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0.6 -2) (end 13.59 -2) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 13.59 19.78) (end -2.16 19.78) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -2.66 4.09) (end -2.66 -2.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 14.09 20.28) (end -2.66 20.28) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -2.66 -2.5) (end 14.09 -2.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 14.09 -2.5) (end 14.09 4.09) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -2.36 19.98) (end -2.36 7.58) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 13.79 4.08) (end 13.79 -2.2) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -2.36 -2.2) (end 13.79 -2.2) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 13.79 19.98) (end 13.79 7.58) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -2.36 4.08) (end -2.36 -2.2) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 13.79 19.98) (end -2.36 19.98) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -2.16 19.78) (end -2.16 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -2.16 15.78) (end 4.21 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 4.21 15.78) (end 4.21 14.28) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 4.21 14.28) (end 7.22 14.28) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 7.22 14.28) (end 7.22 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 7.22 15.78) (end 13.59 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 13.59 15.78) (end 13.59 19.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 13.59 19.78) (end -2.16 19.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -2.16 19.78) (end 1.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -2.16 18.78) (end 0.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -2.16 17.78) (end -0.16 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -2.16 16.78) (end -1.16 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -1.16 19.78) (end 2.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start -0.16 19.78) (end 3.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 3.84 19.78) (end 7.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 4.84 19.78) (end 8.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 5.84 19.78) (end 9.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 6.84 19.78) (end 10.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 7.84 19.78) (end 11.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 8.84 19.78) (end 12.84 15.78) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 1.84 19.78) (end 7.22 14.4) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 0.84 19.77) (end 6.33 14.28) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 2.84 19.77) (end 7.22 15.39) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 9.84 19.78) (end 13.59 16.03) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 10.84 19.77) (end 13.59 17.02) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 11.84 19.77) (end 13.59 18.02) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 12.84 19.77) (end 13.59 19.02) (layer Dwgs.User) (width 0.12))
|
||||
(fp_line (start 4.21 15.41) (end 5.34 14.29) (layer Dwgs.User) (width 0.12))
|
||||
(fp_text user %R (at 6 6) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -2.66 4.09) (end -3.81 4.09) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.81 4.09) (end -3.81 7.59) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.81 7.59) (end -2.66 7.59) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -2.16 19.78) (end -2.16 -2) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -2.66 7.59) (end -2.66 20.28) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 14.09 4.09) (end 15.24 4.09) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 15.24 4.09) (end 15.24 7.59) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 15.24 7.59) (end 14.09 7.59) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 14.09 7.59) (end 14.09 20.28) (layer F.CrtYd) (width 0.05))
|
||||
(pad R1 thru_hole rect (at 0 0) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad R2 thru_hole circle (at 1.27 2.54) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad R3 thru_hole circle (at 2.54 0) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad R4 thru_hole circle (at 3.81 2.54) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad R5 thru_hole circle (at 5.08 0) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad R6 thru_hole circle (at 6.35 2.54) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad R7 thru_hole circle (at 7.62 0) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad R8 thru_hole circle (at 8.89 2.54) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad L1 thru_hole circle (at 12.04 12.27) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad L2 thru_hole circle (at 9.5 13.79) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad L3 thru_hole circle (at 1.93 12.27) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad L4 thru_hole circle (at -0.61 13.79) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad SH thru_hole circle (at -2.06 5.84) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask))
|
||||
(pad SH thru_hole circle (at 13.49 5.84) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask))
|
||||
(pad "" np_thru_hole circle (at 0 8.89) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask))
|
||||
(pad "" np_thru_hole circle (at 11.43 8.89) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask))
|
||||
(pad R9 thru_hole circle (at 10.16 0) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad R10 thru_hole circle (at 11.43 2.54) (size 1.9 1.9) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_RJ.3dshapes/RJ45_UDE_RB1-125B8G1A.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
||||
467
nubus-to-ztex/RB1-125B8G1A.lib
Normal file
467
nubus-to-ztex/RB1-125B8G1A.lib
Normal file
@ -0,0 +1,467 @@
|
||||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# RB1-125B8G1A
|
||||
#
|
||||
DEF RB1-125B8G1A J 0 20 Y N 1 F N
|
||||
F0 "J" -300 800 50 H V C CNN
|
||||
F1 "RB1-125B8G1A" 600 800 50 H V C CNN
|
||||
F2 "Connector_RJ:RJ45_UDE_RB1-125B8G1A" 50 100 50 H I C CNN
|
||||
F3 "" -240 45 50 H I L TNN
|
||||
$FPLIST
|
||||
RJ45*UDE*RB1*125B8G1A*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
A 10 -430 10 1 1799 0 1 0 N 20 -430 0 -430
|
||||
A 10 -370 10 -1799 -1 0 1 0 N 0 -370 20 -370
|
||||
A 10 -130 10 1 1799 0 1 0 N 20 -130 0 -130
|
||||
A 10 -70 10 -1799 -1 0 1 0 N 0 -70 20 -70
|
||||
A 10 170 10 1 1799 0 1 0 N 20 170 0 170
|
||||
A 10 230 10 -1799 -1 0 1 0 N 0 230 20 230
|
||||
A 10 470 10 1 1799 0 1 0 N 20 470 0 470
|
||||
A 10 530 10 -1799 -1 0 1 0 N 0 530 20 530
|
||||
A 30 -430 10 1 1799 0 1 0 N 40 -430 20 -430
|
||||
A 30 -370 10 -1799 -1 0 1 0 N 20 -370 40 -370
|
||||
A 30 -130 10 1 1799 0 1 0 N 40 -130 20 -130
|
||||
A 30 -70 10 -1799 -1 0 1 0 N 20 -70 40 -70
|
||||
A 30 170 10 1 1799 0 1 0 N 40 170 20 170
|
||||
A 30 230 10 -1799 -1 0 1 0 N 20 230 40 230
|
||||
A 30 470 10 1 1799 0 1 0 N 40 470 20 470
|
||||
A 30 530 10 -1799 -1 0 1 0 N 20 530 40 530
|
||||
A 50 -430 10 1 1799 0 1 0 N 60 -430 40 -430
|
||||
A 50 -370 10 -1799 -1 0 1 0 N 40 -370 60 -370
|
||||
A 50 -130 10 1 1799 0 1 0 N 60 -130 40 -130
|
||||
A 50 -70 10 -1799 -1 0 1 0 N 40 -70 60 -70
|
||||
A 50 170 10 1 1799 0 1 0 N 60 170 40 170
|
||||
A 50 230 10 -1799 -1 0 1 0 N 40 230 60 230
|
||||
A 50 470 10 1 1799 0 1 0 N 60 470 40 470
|
||||
A 50 530 10 -1799 -1 0 1 0 N 40 530 60 530
|
||||
A 70 -430 10 1 1799 0 1 0 N 80 -430 60 -430
|
||||
A 70 -370 10 -1799 -1 0 1 0 N 60 -370 80 -370
|
||||
A 70 -130 10 1 1799 0 1 0 N 80 -130 60 -130
|
||||
A 70 -70 10 -1799 -1 0 1 0 N 60 -70 80 -70
|
||||
A 70 170 10 1 1799 0 1 0 N 80 170 60 170
|
||||
A 70 230 10 -1799 -1 0 1 0 N 60 230 80 230
|
||||
A 70 470 10 1 1799 0 1 0 N 80 470 60 470
|
||||
A 70 530 10 -1799 -1 0 1 0 N 60 530 80 530
|
||||
A 200 -470 10 -899 899 0 1 0 N 200 -480 200 -460
|
||||
A 200 -450 10 -899 899 0 1 0 N 200 -460 200 -440
|
||||
A 200 -430 10 -899 899 0 1 0 N 200 -440 200 -420
|
||||
A 200 -410 10 -899 899 0 1 0 N 200 -420 200 -400
|
||||
A 200 -390 10 -899 899 0 1 0 N 200 -400 200 -380
|
||||
A 200 -370 10 -899 899 0 1 0 N 200 -380 200 -360
|
||||
A 200 -350 10 -899 899 0 1 0 N 200 -360 200 -340
|
||||
A 200 -330 10 -899 899 0 1 0 N 200 -340 200 -320
|
||||
A 200 -170 10 -899 899 0 1 0 N 200 -180 200 -160
|
||||
A 200 -150 10 -899 899 0 1 0 N 200 -160 200 -140
|
||||
A 200 -130 10 -899 899 0 1 0 N 200 -140 200 -120
|
||||
A 200 -110 10 -899 899 0 1 0 N 200 -120 200 -100
|
||||
A 200 -90 10 -899 899 0 1 0 N 200 -100 200 -80
|
||||
A 200 -70 10 -899 899 0 1 0 N 200 -80 200 -60
|
||||
A 200 -50 10 -899 899 0 1 0 N 200 -60 200 -40
|
||||
A 200 -30 10 -899 899 0 1 0 N 200 -40 200 -20
|
||||
A 200 130 10 -899 899 0 1 0 N 200 120 200 140
|
||||
A 200 150 10 -899 899 0 1 0 N 200 140 200 160
|
||||
A 200 170 10 -899 899 0 1 0 N 200 160 200 180
|
||||
A 200 190 10 -899 899 0 1 0 N 200 180 200 200
|
||||
A 200 210 10 -899 899 0 1 0 N 200 200 200 220
|
||||
A 200 230 10 -899 899 0 1 0 N 200 220 200 240
|
||||
A 200 250 10 -899 899 0 1 0 N 200 240 200 260
|
||||
A 200 270 10 -899 899 0 1 0 N 200 260 200 280
|
||||
A 200 430 10 -899 899 0 1 0 N 200 420 200 440
|
||||
A 200 450 10 -899 899 0 1 0 N 200 440 200 460
|
||||
A 200 470 10 -899 899 0 1 0 N 200 460 200 480
|
||||
A 200 490 10 -899 899 0 1 0 N 200 480 200 500
|
||||
A 200 510 10 -899 899 0 1 0 N 200 500 200 520
|
||||
A 200 530 10 -899 899 0 1 0 N 200 520 200 540
|
||||
A 200 550 10 -899 899 0 1 0 N 200 540 200 560
|
||||
A 200 570 10 -899 899 0 1 0 N 200 560 200 580
|
||||
A 250 -470 10 901 -901 0 1 0 N 250 -460 250 -480
|
||||
A 250 -450 10 901 -901 0 1 0 N 250 -440 250 -460
|
||||
A 250 -430 10 901 -901 0 1 0 N 250 -420 250 -440
|
||||
A 250 -410 10 901 -901 0 1 0 N 250 -400 250 -420
|
||||
A 250 -390 10 901 -901 0 1 0 N 250 -380 250 -400
|
||||
A 250 -370 10 901 -901 0 1 0 N 250 -360 250 -380
|
||||
A 250 -350 10 901 -901 0 1 0 N 250 -340 250 -360
|
||||
A 250 -330 10 901 -901 0 1 0 N 250 -320 250 -340
|
||||
A 250 -170 10 901 -901 0 1 0 N 250 -160 250 -180
|
||||
A 250 -150 10 901 -901 0 1 0 N 250 -140 250 -160
|
||||
A 250 -130 10 901 -901 0 1 0 N 250 -120 250 -140
|
||||
A 250 -110 10 901 -901 0 1 0 N 250 -100 250 -120
|
||||
A 250 -90 10 901 -901 0 1 0 N 250 -80 250 -100
|
||||
A 250 -70 10 901 -901 0 1 0 N 250 -60 250 -80
|
||||
A 250 -50 10 901 -901 0 1 0 N 250 -40 250 -60
|
||||
A 250 -30 10 901 -901 0 1 0 N 250 -20 250 -40
|
||||
A 250 130 10 901 -901 0 1 0 N 250 140 250 120
|
||||
A 250 150 10 901 -901 0 1 0 N 250 160 250 140
|
||||
A 250 170 10 901 -901 0 1 0 N 250 180 250 160
|
||||
A 250 190 10 901 -901 0 1 0 N 250 200 250 180
|
||||
A 250 210 10 901 -901 0 1 0 N 250 220 250 200
|
||||
A 250 230 10 901 -901 0 1 0 N 250 240 250 220
|
||||
A 250 250 10 901 -901 0 1 0 N 250 260 250 240
|
||||
A 250 270 10 901 -901 0 1 0 N 250 280 250 260
|
||||
A 250 430 10 901 -901 0 1 0 N 250 440 250 420
|
||||
A 250 450 10 901 -901 0 1 0 N 250 460 250 440
|
||||
A 250 470 10 901 -901 0 1 0 N 250 480 250 460
|
||||
A 250 490 10 901 -901 0 1 0 N 250 500 250 480
|
||||
A 250 510 10 901 -901 0 1 0 N 250 520 250 500
|
||||
A 250 530 10 901 -901 0 1 0 N 250 540 250 520
|
||||
A 250 550 10 901 -901 0 1 0 N 250 560 250 540
|
||||
A 250 570 10 901 -901 0 1 0 N 250 580 250 560
|
||||
C -100 -470 10 0 1 0 F
|
||||
C -100 -170 10 0 1 0 F
|
||||
C -100 130 10 0 1 0 F
|
||||
C 70 -431 3 0 1 1 F
|
||||
C 70 -369 3 0 1 1 F
|
||||
C 70 -131 3 0 1 1 F
|
||||
C 70 -69 3 0 1 1 F
|
||||
C 70 169 3 0 1 1 F
|
||||
C 70 231 3 0 1 1 F
|
||||
C 70 469 3 0 1 1 F
|
||||
C 70 531 3 0 1 1 F
|
||||
C 199 -410 3 0 1 1 F
|
||||
C 199 -330 3 0 1 1 F
|
||||
C 199 -110 3 0 1 1 F
|
||||
C 199 -30 3 0 1 1 F
|
||||
C 199 190 3 0 1 1 F
|
||||
C 199 270 3 0 1 1 F
|
||||
C 199 490 3 0 1 1 F
|
||||
C 199 570 3 0 1 1 F
|
||||
C 251 -410 3 0 1 1 F
|
||||
C 251 -330 3 0 1 1 F
|
||||
C 251 -110 3 0 1 1 F
|
||||
C 251 -30 3 0 1 1 F
|
||||
C 251 190 3 0 1 1 F
|
||||
C 251 270 3 0 1 1 F
|
||||
C 251 490 3 0 1 1 F
|
||||
C 251 570 3 0 1 1 F
|
||||
C 300 -100 10 0 1 0 F
|
||||
C 300 200 10 0 1 0 F
|
||||
C 300 500 10 0 1 0 F
|
||||
T 0 100 -540 25 0 0 0 "1000pF 2kV" Normal 0 C C
|
||||
T 0 30 -470 25 0 0 0 75 Normal 0 C C
|
||||
T 0 30 -170 25 0 0 0 75 Normal 0 C C
|
||||
T 0 30 130 25 0 0 0 75 Normal 0 C C
|
||||
T 0 30 430 25 0 0 0 75 Normal 0 C C
|
||||
T 0 -200 550 50 0 0 0 C1 Normal 0 C C
|
||||
T 0 -200 460 50 0 0 0 C2 Normal 0 C C
|
||||
T 0 -200 240 50 0 0 0 C3 Normal 0 C C
|
||||
T 0 -200 -60 50 0 0 0 C4 Normal 0 C C
|
||||
T 0 -200 -140 50 0 0 0 C5 Normal 0 C C
|
||||
T 0 -200 160 50 0 0 0 C6 Normal 0 C C
|
||||
T 0 -200 -360 50 0 0 0 C7 Normal 0 C C
|
||||
T 0 -200 -440 50 0 0 0 C8 Normal 0 C C
|
||||
T 0 -100 650 50 0 0 0 G Normal 0 C C
|
||||
T 0 100 650 50 0 0 0 Y Normal 0 C C
|
||||
S -150 -480 -250 590 0 1 0 N
|
||||
S -20 -490 80 -450 0 1 8 N
|
||||
S -20 -190 80 -150 0 1 8 N
|
||||
S -20 110 80 150 0 1 8 N
|
||||
S -20 410 80 450 0 1 8 N
|
||||
S 350 750 -300 -650 0 1 10 f
|
||||
P 2 0 0 0 -20 -470 -100 -470 N
|
||||
P 2 0 0 0 0 -430 -150 -430 N
|
||||
P 2 0 0 0 0 -370 -150 -370 N
|
||||
P 2 0 0 0 0 -130 -150 -130 N
|
||||
P 2 0 0 0 0 -70 -150 -70 N
|
||||
P 2 0 0 0 0 170 -150 170 N
|
||||
P 2 0 0 0 0 230 -150 230 N
|
||||
P 2 0 0 0 0 470 -150 470 N
|
||||
P 2 0 0 0 0 530 -150 530 N
|
||||
P 2 0 0 0 250 200 300 200 N
|
||||
P 2 0 0 0 300 -100 250 -100 N
|
||||
P 2 0 0 0 300 500 250 500 N
|
||||
P 4 0 0 0 80 -470 150 -470 150 -400 200 -400 N
|
||||
P 4 0 0 0 80 -170 150 -170 150 -100 200 -100 N
|
||||
P 4 0 0 0 80 130 150 130 150 200 200 200 N
|
||||
P 4 0 0 0 80 430 150 430 150 500 200 500 N
|
||||
P 2 0 1 13 -130 -550 -70 -550 N
|
||||
P 2 0 1 12 -130 -530 -70 -530 N
|
||||
P 2 0 1 0 -100 -650 -100 -550 N
|
||||
P 2 0 1 0 -100 130 -20 130 N
|
||||
P 2 0 1 0 -40 670 -60 690 N
|
||||
P 2 0 1 0 -30 740 -30 700 N
|
||||
P 2 0 1 0 -20 -170 -100 -170 N
|
||||
P 2 0 1 0 -20 670 -40 690 N
|
||||
P 2 0 1 0 0 -410 80 -410 N
|
||||
P 2 0 1 0 0 -110 80 -110 N
|
||||
P 2 0 1 0 0 190 80 190 N
|
||||
P 2 0 1 0 0 490 80 490 N
|
||||
P 2 0 1 0 80 -390 0 -390 N
|
||||
P 2 0 1 0 80 -90 0 -90 N
|
||||
P 2 0 1 0 80 210 0 210 N
|
||||
P 2 0 1 0 80 510 0 510 N
|
||||
P 2 0 1 0 160 670 140 690 N
|
||||
P 2 0 1 0 170 740 170 700 N
|
||||
P 2 0 1 0 180 670 160 690 N
|
||||
P 2 0 1 0 220 -320 220 -480 N
|
||||
P 2 0 1 0 220 -20 220 -180 N
|
||||
P 2 0 1 0 220 280 220 120 N
|
||||
P 2 0 1 0 220 580 220 420 N
|
||||
P 2 0 1 0 230 -480 230 -320 N
|
||||
P 2 0 1 0 230 -180 230 -20 N
|
||||
P 2 0 1 0 230 120 230 280 N
|
||||
P 2 0 1 0 230 420 230 580 N
|
||||
P 3 0 1 0 -100 -530 -100 430 -20 430 N
|
||||
P 3 0 1 0 -100 750 -100 720 -70 720 N
|
||||
P 3 0 1 0 -40 680 -40 670 -50 670 N
|
||||
P 3 0 1 0 -20 680 -20 670 -30 670 N
|
||||
P 3 0 1 0 0 750 0 720 -30 720 N
|
||||
P 3 0 1 0 100 750 100 720 130 720 N
|
||||
P 3 0 1 0 160 680 160 670 150 670 N
|
||||
P 3 0 1 0 180 680 180 670 170 670 N
|
||||
P 3 0 1 0 200 750 200 720 170 720 N
|
||||
P 3 0 1 0 250 -480 250 -500 350 -500 N
|
||||
P 3 0 1 0 250 -320 250 -300 350 -300 N
|
||||
P 3 0 1 0 250 -180 250 -200 350 -200 N
|
||||
P 3 0 1 0 250 -20 250 0 350 0 N
|
||||
P 3 0 1 0 250 120 250 100 350 100 N
|
||||
P 3 0 1 0 250 280 250 300 350 300 N
|
||||
P 3 0 1 0 250 420 250 400 350 400 N
|
||||
P 3 0 1 0 250 580 250 600 350 600 N
|
||||
P 4 0 1 0 -30 720 -70 740 -70 700 -30 720 N
|
||||
P 4 0 1 0 170 720 130 740 130 700 170 720 N
|
||||
P 4 0 1 0 350 700 300 700 300 -400 250 -400 N
|
||||
P 5 0 1 0 80 -370 100 -370 100 -300 200 -300 200 -320 N
|
||||
P 5 0 1 0 80 -70 100 -70 100 0 200 0 200 -20 N
|
||||
P 5 0 1 0 80 230 100 230 100 300 200 300 200 280 N
|
||||
P 5 0 1 0 80 530 100 530 100 600 200 600 200 580 N
|
||||
P 5 0 1 0 200 -480 200 -500 100 -500 100 -430 80 -430 N
|
||||
P 5 0 1 0 200 -180 200 -200 100 -200 100 -130 80 -130 N
|
||||
P 5 0 1 0 200 120 200 100 100 100 100 170 80 170 N
|
||||
P 5 0 1 0 200 420 200 400 100 400 100 470 80 470 N
|
||||
X GND R10 -100 -800 150 U 50 50 0 1 W
|
||||
X ~ L1 100 900 150 D 50 50 1 1 P
|
||||
X ~ L2 200 900 150 D 50 50 1 1 P
|
||||
X ~ L3 -100 900 150 D 50 50 1 1 P
|
||||
X ~ L4 0 900 150 D 50 50 1 1 P
|
||||
X CT R1 500 700 150 L 50 50 1 1 P
|
||||
X TD1+ R2 500 600 150 L 50 50 1 1 P
|
||||
X TD1- R3 500 400 150 L 50 50 1 1 P
|
||||
X TD2+ R4 500 300 150 L 50 50 1 1 P
|
||||
X TD2- R5 500 100 150 L 50 50 1 1 P
|
||||
X TD3+ R6 500 0 150 L 50 50 1 1 P
|
||||
X TD3- R7 500 -200 150 L 50 50 1 1 P
|
||||
X TD4+ R8 500 -300 150 L 50 50 1 1 P
|
||||
X TD4- R9 500 -500 150 L 50 50 1 1 P
|
||||
X SH SH 100 -800 150 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# RJ45_Abracon_ARJP11A-MASA-B-A-EMU2
|
||||
#
|
||||
DEF RJ45_Abracon_ARJP11A-MASA-B-A-EMU2 J 0 40 Y N 1 F N
|
||||
F0 "J" 0 -1500 50 H V C CNN
|
||||
F1 "RJ45_Abracon_ARJP11A-MASA-B-A-EMU2" 0 -1400 50 H V C CNN
|
||||
F2 "Connector_RJ:RJ45_Abracon_ARJP11A-MA_Horizontal" 0 1400 50 H I C CNN
|
||||
F3 "" -150 -850 50 H I C CNN
|
||||
$FPLIST
|
||||
RJ45*Abracon*ARJP11A?MA*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
A -250 -625 25 -899 899 0 1 0 N -250 -650 -250 -600
|
||||
A -250 -600 50 900 900 0 1 0 N -250 -550 -250 -550
|
||||
A -250 -575 25 -899 899 0 1 0 N -250 -600 -250 -550
|
||||
A -250 -425 25 -899 899 0 1 0 N -250 -450 -250 -400
|
||||
A -250 -775 25 -899 899 1 1 0 N -250 -800 -250 -750
|
||||
A -250 -750 50 900 900 1 1 0 N -250 -700 -250 -700
|
||||
A -250 -725 25 -899 899 1 1 0 N -250 -750 -250 -700
|
||||
A -250 -675 25 -899 899 1 1 0 N -250 -700 -250 -650
|
||||
A -250 -525 25 -899 899 1 1 0 N -250 -550 -250 -500
|
||||
A -250 -475 25 -899 899 1 1 0 N -250 -500 -250 -450
|
||||
A -250 -275 25 -899 899 1 1 0 N -250 -300 -250 -250
|
||||
A -250 -250 50 900 900 1 1 0 N -250 -200 -250 -200
|
||||
A -250 -225 25 -899 899 1 1 0 N -250 -250 -250 -200
|
||||
A -250 -200 50 900 900 1 1 0 N -250 -150 -250 -150
|
||||
A -250 -175 25 -899 899 1 1 0 N -250 -200 -250 -150
|
||||
A -250 -125 25 -899 899 1 1 0 N -250 -150 -250 -100
|
||||
A -250 -75 25 -899 899 1 1 0 N -250 -100 -250 -50
|
||||
A -250 -25 25 -899 899 1 1 0 N -250 -50 -250 0
|
||||
A -250 0 50 900 900 1 1 0 N -250 50 -250 50
|
||||
A -250 25 25 -899 899 1 1 0 N -250 0 -250 50
|
||||
A -250 75 25 -899 899 1 1 0 N -250 50 -250 100
|
||||
A -100 -775 25 901 -901 1 1 0 N -100 -750 -100 -800
|
||||
A -100 -725 25 901 -901 1 1 0 N -100 -700 -100 -750
|
||||
A -100 -700 50 -900 -900 1 1 0 N -100 -750 -100 -750
|
||||
A -100 -675 25 901 -901 1 1 0 N -100 -650 -100 -700
|
||||
A -100 -625 25 901 -901 1 1 0 N -100 -600 -100 -650
|
||||
A -100 -575 25 901 -901 1 1 0 N -100 -550 -100 -600
|
||||
A -100 -550 50 -900 -900 1 1 0 N -100 -600 -100 -600
|
||||
A -100 -525 25 901 -901 1 1 0 N -100 -500 -100 -550
|
||||
A -100 -475 25 901 -901 1 1 0 N -100 -450 -100 -500
|
||||
A -100 -425 25 901 -901 1 1 0 N -100 -400 -100 -450
|
||||
A -100 -275 25 901 -901 1 1 0 N -100 -250 -100 -300
|
||||
A -100 -225 25 901 -901 1 1 0 N -100 -200 -100 -250
|
||||
A -100 -200 50 -900 -900 1 1 0 N -100 -250 -100 -250
|
||||
A -100 -175 25 901 -901 1 1 0 N -100 -150 -100 -200
|
||||
A -100 -125 25 901 -901 1 1 0 N -100 -100 -100 -150
|
||||
A -100 -100 50 -900 -900 1 1 0 N -100 -150 -100 -150
|
||||
A -100 -75 25 901 -901 1 1 0 N -100 -50 -100 -100
|
||||
A -100 -25 25 901 -901 1 1 0 N -100 0 -100 -50
|
||||
A -100 25 25 901 -901 1 1 0 N -100 50 -100 0
|
||||
A -100 50 50 -900 -900 1 1 0 N -100 0 -100 0
|
||||
A -100 75 25 901 -901 1 1 0 N -100 100 -100 50
|
||||
A 100 -550 50 0 0 1 1 0 N 150 -550 150 -550
|
||||
A 100 0 50 0 0 1 1 0 N 150 0 150 0
|
||||
A 125 -700 25 1 1799 1 1 0 N 150 -700 100 -700
|
||||
A 125 -700 25 1 1799 1 1 0 N 150 -700 100 -700
|
||||
A 125 -550 25 -1799 -1 1 1 0 N 100 -550 150 -550
|
||||
A 125 -550 25 -1799 -1 1 1 0 N 100 -550 150 -550
|
||||
A 125 -150 25 1 1799 1 1 0 N 150 -150 100 -150
|
||||
A 125 -150 25 1 1799 1 1 0 N 150 -150 100 -150
|
||||
A 125 0 25 -1799 -1 1 1 0 N 100 0 150 0
|
||||
A 125 0 25 -1799 -1 1 1 0 N 100 0 150 0
|
||||
A 150 -700 50 1800 1800 1 1 0 N 100 -700 100 -700
|
||||
A 150 -150 50 1800 1800 1 1 0 N 100 -150 100 -150
|
||||
A 175 -700 25 1 1799 1 1 0 N 200 -700 150 -700
|
||||
A 175 -550 25 -1799 -1 1 1 0 N 150 -550 200 -550
|
||||
A 175 -150 25 1 1799 1 1 0 N 200 -150 150 -150
|
||||
A 175 0 25 -1799 -1 1 1 0 N 150 0 200 0
|
||||
A 200 -550 50 0 0 1 1 0 N 250 -550 250 -550
|
||||
A 200 0 50 0 0 1 1 0 N 250 0 250 0
|
||||
A 225 -700 25 1 1799 1 1 0 N 250 -700 200 -700
|
||||
A 225 -700 25 1 1799 1 1 0 N 250 -700 200 -700
|
||||
A 225 -550 25 -1799 -1 1 1 0 N 200 -550 250 -550
|
||||
A 225 -550 25 -1799 -1 1 1 0 N 200 -550 250 -550
|
||||
A 225 -150 25 1 1799 1 1 0 N 250 -150 200 -150
|
||||
A 225 -150 25 1 1799 1 1 0 N 250 -150 200 -150
|
||||
A 225 0 25 -1799 -1 1 1 0 N 200 0 250 0
|
||||
A 225 0 25 -1799 -1 1 1 0 N 200 0 250 0
|
||||
A 250 -700 50 1800 1800 1 1 0 N 200 -700 200 -700
|
||||
A 250 -150 50 1800 1800 1 1 0 N 200 -150 200 -150
|
||||
A 275 -700 25 1 1799 1 1 0 N 300 -700 250 -700
|
||||
A 275 -550 25 -1799 -1 1 1 0 N 250 -550 300 -550
|
||||
A 275 -150 25 1 1799 1 1 0 N 300 -150 250 -150
|
||||
A 275 0 25 -1799 -1 1 1 0 N 250 0 300 0
|
||||
C 50 300 0 0 0 20 N
|
||||
C -450 300 0 1 1 20 N
|
||||
C -200 700 0 1 1 20 N
|
||||
C 50 500 0 1 1 20 N
|
||||
C 200 900 0 1 1 20 N
|
||||
C 200 900 0 1 1 20 N
|
||||
C 250 950 0 1 1 20 N
|
||||
C 250 1250 0 1 1 20 N
|
||||
T 0 450 -750 50 0 0 0 "1 TX+" Normal 0 C C
|
||||
T 0 450 -450 50 0 0 0 "2 TX-" Normal 0 C C
|
||||
T 0 450 -250 50 0 0 0 "3 RX+" Normal 0 C C
|
||||
T 0 350 900 50 0 0 0 4 Normal 0 C C
|
||||
T 0 350 1000 50 0 0 0 5 Normal 0 C C
|
||||
T 0 450 50 50 0 0 0 "6 RX-" Normal 0 C C
|
||||
T 0 350 1200 50 0 0 0 7 Normal 0 C C
|
||||
T 0 350 1300 50 0 0 0 8 Normal 0 C C
|
||||
T 0 -550 -50 50 0 0 0 CT Normal 0 L C
|
||||
T 0 50 -950 50 0 0 0 "LEFT LED" Normal 0 C C
|
||||
T 0 -550 150 50 0 0 0 RD- Normal 0 L C
|
||||
T 0 450 -1100 50 0 0 0 SHIELD Normal 0 C C
|
||||
T 0 -550 750 50 0 0 0 V+ Normal 0 L C
|
||||
T 0 -550 950 50 0 0 0 V- Normal 0 L C
|
||||
T 0 -550 -550 50 0 1 1 CT Normal 0 L C
|
||||
T 0 -550 -250 50 0 1 1 RD+ Normal 0 L C
|
||||
T 0 50 -1150 50 0 1 1 "RIGHT LED" Normal 0 C C
|
||||
T 0 -550 -750 50 0 1 1 TD+ Normal 0 L C
|
||||
T 0 -550 -350 50 0 1 1 TD- Normal 0 L C
|
||||
S -600 -1350 600 1350 0 0 10 f
|
||||
S -150 350 -400 250 0 0 0 N
|
||||
S -150 550 -400 450 1 1 0 N
|
||||
P 2 0 0 0 -600 -1300 -400 -1300 N
|
||||
P 2 0 0 0 -600 -1200 -400 -1200 N
|
||||
P 2 0 0 0 -600 -1100 -400 -1100 N
|
||||
P 2 0 0 0 -600 -1000 -400 -1000 N
|
||||
P 2 0 0 0 -600 -800 -400 -800 N
|
||||
P 2 0 0 0 -600 -600 -400 -600 N
|
||||
P 2 0 0 0 -600 -400 -400 -400 N
|
||||
P 2 0 0 0 -600 -300 -400 -300 N
|
||||
P 2 0 0 0 -600 -100 -400 -100 N
|
||||
P 2 0 0 0 -600 100 -400 100 N
|
||||
P 2 0 0 0 -600 900 200 900 N
|
||||
P 2 0 0 0 -450 300 -600 300 N
|
||||
P 2 0 0 0 -440 -1000 -290 -1000 N
|
||||
P 2 0 0 0 -400 300 -450 300 N
|
||||
P 2 0 0 0 -200 700 -600 700 N
|
||||
P 2 0 0 0 -200 700 -150 700 N
|
||||
P 2 0 0 0 -200 750 -200 700 N
|
||||
P 2 0 0 0 -150 300 -100 300 N
|
||||
P 2 0 0 0 -150 500 -100 500 N
|
||||
P 2 0 0 0 -100 350 -100 250 N
|
||||
P 2 0 0 0 -50 350 -50 250 N
|
||||
P 2 0 0 0 -50 550 -50 450 N
|
||||
P 2 0 0 0 0 850 250 850 N
|
||||
P 2 0 0 0 0 950 400 950 N
|
||||
P 2 0 0 0 0 1250 400 1250 N
|
||||
P 2 0 0 0 50 400 50 500 N
|
||||
P 3 0 0 0 -400 500 -450 500 -450 300 N
|
||||
P 3 0 0 0 -150 1100 -200 1100 -200 700 N
|
||||
P 3 0 0 0 -50 500 0 500 50 500 N
|
||||
P 3 0 0 0 50 500 250 500 250 850 N
|
||||
P 3 0 0 0 250 950 250 1050 400 1050 N
|
||||
P 3 0 0 0 250 1250 250 1150 400 1150 N
|
||||
P 4 0 0 0 -190 -1000 -90 -1000 -90 -1100 -440 -1100 N
|
||||
P 4 0 0 0 -100 -600 -50 -600 50 -600 50 400 N
|
||||
P 4 0 0 0 150 700 200 700 200 1100 150 1100 N
|
||||
P 5 0 0 0 -150 700 0 550 150 700 0 850 -150 700 N
|
||||
P 2 0 1 0 -250 -800 -400 -800 N
|
||||
P 2 0 1 0 -250 -600 -400 -600 N
|
||||
P 2 0 1 0 -250 -400 -400 -400 N
|
||||
P 2 0 1 0 -250 -300 -400 -300 N
|
||||
P 2 0 1 0 -250 -100 -400 -100 N
|
||||
P 2 0 1 0 -250 100 -400 100 N
|
||||
P 2 0 1 0 -240 -1120 -250 -1120 N
|
||||
P 2 0 1 0 -210 -1140 -220 -1140 N
|
||||
P 2 0 1 0 -190 -950 -190 -1050 N
|
||||
P 2 0 1 0 -50 300 50 300 N
|
||||
P 2 0 1 0 -25 700 -150 700 N
|
||||
P 2 0 1 0 -25 750 -25 650 N
|
||||
P 2 0 1 0 25 700 150 700 N
|
||||
P 3 0 1 0 -260 -1140 -240 -1120 -240 -1130 N
|
||||
P 3 0 1 0 -230 -1160 -210 -1140 -210 -1150 N
|
||||
P 4 0 1 0 -290 -950 -290 -1050 -190 -1000 -290 -950 N
|
||||
P 4 0 1 0 25 750 25 650 -25 700 25 750 N
|
||||
P 2 1 1 0 -440 -1200 -290 -1200 N
|
||||
P 2 1 1 0 -240 -920 -250 -920 N
|
||||
P 2 1 1 0 -210 -940 -220 -940 N
|
||||
P 2 1 1 0 -200 -400 -200 -800 N
|
||||
P 2 1 1 0 -200 100 -200 -300 N
|
||||
P 2 1 1 0 -190 -1150 -190 -1250 N
|
||||
P 2 1 1 0 -150 -800 -150 -400 N
|
||||
P 2 1 1 0 -150 -300 -150 100 N
|
||||
P 2 1 1 0 -100 550 -100 450 N
|
||||
P 2 1 1 0 -25 1100 -150 1100 N
|
||||
P 2 1 1 0 -25 1150 -25 1050 N
|
||||
P 2 1 1 0 25 1100 150 1100 N
|
||||
P 2 1 1 0 100 -650 300 -650 N
|
||||
P 2 1 1 0 100 -600 300 -100 N
|
||||
P 2 1 1 0 100 -100 300 -100 N
|
||||
P 2 1 1 0 300 -600 100 -600 N
|
||||
P 2 1 1 0 300 -50 100 -50 N
|
||||
P 3 1 1 0 -260 -940 -240 -920 -240 -930 N
|
||||
P 3 1 1 0 -230 -960 -210 -940 -210 -950 N
|
||||
P 3 1 1 0 -100 -400 100 -400 100 -550 N
|
||||
P 3 1 1 0 -100 -300 100 -300 100 -150 N
|
||||
P 3 1 1 0 -100 100 100 100 100 0 N
|
||||
P 3 1 1 0 100 -700 100 -800 -100 -800 N
|
||||
P 3 1 1 0 300 -700 300 -800 400 -800 N
|
||||
P 3 1 1 0 300 -550 300 -400 400 -400 N
|
||||
P 3 1 1 0 300 -150 300 -300 400 -300 N
|
||||
P 3 1 1 0 300 0 300 100 400 100 N
|
||||
P 4 1 1 0 -290 -1150 -290 -1250 -190 -1200 -290 -1150 N
|
||||
P 4 1 1 0 -190 -1200 -90 -1200 -90 -1300 -440 -1300 N
|
||||
P 4 1 1 0 25 1150 25 1050 -25 1100 25 1150 N
|
||||
P 5 1 1 0 -150 1100 0 950 150 1100 0 1250 -150 1100 N
|
||||
X TD+ 1 -700 -800 100 R 50 50 1 1 P
|
||||
X V- 10 -700 900 100 R 50 50 1 1 w
|
||||
X LLED+ 11 -700 -1000 100 R 50 50 1 1 P
|
||||
X LLED- 12 -700 -1100 100 R 50 50 1 1 P
|
||||
X RLED+ 13 -700 -1200 100 R 50 50 1 1 P
|
||||
X RLED- 14 -700 -1300 100 R 50 50 1 1 P
|
||||
X SHIELD 15 700 -1100 100 L 50 50 1 1 P
|
||||
X TD- 2 -700 -400 100 R 50 50 1 1 P
|
||||
X RD+ 3 -700 -300 100 R 50 50 1 1 P
|
||||
X CT 4 -700 -600 100 R 50 50 1 1 P
|
||||
X CT 5 -700 -100 100 R 50 50 1 1 P
|
||||
X RD- 6 -700 100 100 R 50 50 1 1 P
|
||||
X 7 7 -700 300 100 R 50 50 1 1 P
|
||||
X V+ 9 -700 700 100 R 50 50 1 1 w
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -2555,4 +2555,14 @@ Text Notes 350 13400 0 50 ~ 0
|
||||
For ID, it's likely all Macs are using open/ground,\nso we could pull-up to +3V3 and avoid the level shifter entirely.
|
||||
Text Notes 6400 13700 0 50 ~ 0
|
||||
always enabled
|
||||
Wire Notes Line
|
||||
6950 8450 7850 8450
|
||||
Wire Notes Line
|
||||
7850 8450 7850 9300
|
||||
Wire Notes Line
|
||||
7850 9300 6950 9300
|
||||
Wire Notes Line
|
||||
6950 9300 6950 8450
|
||||
Text Notes 6750 8450 0 50 ~ 0
|
||||
signals formerly from FPGA to CPLD\nTBC they are no longer needed
|
||||
$EndSCHEMATC
|
||||
|
||||
Loading…
Reference in New Issue
Block a user