From d9c21e7abbea176d2bf38dcbf5537dbb57be1b75 Mon Sep 17 00:00:00 2001 From: Romain Dolbeau Date: Sat, 4 Jun 2022 18:56:41 +0200 Subject: [PATCH] stat module --- nubus-to-ztex-gateware/nubus_full.py | 5 +++ nubus-to-ztex-gateware/nubus_master_tst.py | 2 +- nubus-to-ztex-gateware/nubus_stat.py | 45 +++++++++++++++++++++ nubus-to-ztex-gateware/nubus_to_fpga_soc.py | 6 +++ 4 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 nubus-to-ztex-gateware/nubus_stat.py diff --git a/nubus-to-ztex-gateware/nubus_full.py b/nubus-to-ztex-gateware/nubus_full.py index 2e3a7b1..e2b028d 100644 --- a/nubus-to-ztex-gateware/nubus_full.py +++ b/nubus-to-ztex-gateware/nubus_full.py @@ -121,6 +121,9 @@ class NuBus(Module): o_block = decoded_block, o_busy = decoded_busy, ) + + self.read_ctr = read_ctr = Signal(32) + self.writ_ctr = writ_ctr = Signal(32) self.submodules.slave_fsm = slave_fsm = ClockDomainsRenamer(cd_nubus)(FSM(reset_state="Reset")) slave_fsm.act("Reset", @@ -135,6 +138,7 @@ class NuBus(Module): #NextValue(current_block, decoded_block), #If(decoded_block, # NextValue(decoded_block_memory, 1),), + NextValue(read_ctr, read_ctr + 1), NextState("WaitWBRead"), ).Elif(decoded_myslot & sampled_start & ~sampled_ack & sampled_tm1,# & ~decoded_block, # regular write NextValue(current_adr, processed_ad), @@ -145,6 +149,7 @@ class NuBus(Module): #If(decoded_block, # NextValue(decoded_block_memory, 1),), #NextState("GetNubusWriteData"), + NextValue(writ_ctr, writ_ctr + 1), NextState("NubusWriteDataToFIFO"), ) ) diff --git a/nubus-to-ztex-gateware/nubus_master_tst.py b/nubus-to-ztex-gateware/nubus_master_tst.py index 998f347..ba3abf3 100644 --- a/nubus-to-ztex-gateware/nubus_master_tst.py +++ b/nubus-to-ztex-gateware/nubus_master_tst.py @@ -68,7 +68,7 @@ class PingMaster(Module): writer_fsm.act("Reset", NextState("Idle"),) writer_fsm.act("Idle", - If(do_write, # & ~nubus.slave_in_use, + If(do_write, NextValue(do_write, 0), bus_mst.cyc.eq(1), bus_mst.stb.eq(1), diff --git a/nubus-to-ztex-gateware/nubus_stat.py b/nubus-to-ztex-gateware/nubus_stat.py new file mode 100644 index 0000000..9b12e70 --- /dev/null +++ b/nubus-to-ztex-gateware/nubus_stat.py @@ -0,0 +1,45 @@ +from migen import * +from migen.genlib.fifo import * +from migen.genlib.cdc import BusSynchronizer + +import litex +from litex.soc.interconnect import wishbone + +class NuBusStat(Module): + def __init__(self, nubus, platform): + self.bus_slv = bus_slv = wishbone.Interface() + + read_ctr = Signal(32) + writ_ctr = Signal(32) + + self.submodules.sync_read_ctr = BusSynchronizer(width = 32, idomain="nubus", odomain="sys") + self.submodules.sync_writ_ctr = BusSynchronizer(width = 32, idomain="nubus", odomain="sys") + self.comb += [ + self.sync_read_ctr.i.eq(nubus.read_ctr), + read_ctr.eq(self.sync_read_ctr.o), + self.sync_writ_ctr.i.eq(nubus.writ_ctr), + writ_ctr.eq(self.sync_writ_ctr.o), + ] + + self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset") + wishbone_fsm.act("Reset", + NextValue(bus_slv.ack, 0), + NextState("Idle")) + wishbone_fsm.act("Idle", + If(bus_slv.cyc & bus_slv.stb & bus_slv.we & ~bus_slv.ack, #write + # FIXME: should check for prefix? + #Case(bus_slv.adr[0:10], { + # 0x0: [ NextValue(read_ctr, bus_slv.dat_w[0:32]), ], + # 0x1: [ NextValue(write_ctr, bus_slv.dat_w[0:32]), ], + #}), + NextValue(bus_slv.ack, 1), + ).Elif(bus_slv.cyc & bus_slv.stb & ~bus_slv.we & ~bus_slv.ack, #read + Case(bus_slv.adr[0:10], { + 0x0: [ NextValue(bus_slv.dat_r, Cat(read_ctr[24:32], read_ctr[16:24], read_ctr[ 8:16], read_ctr[ 0: 8])), ], + 0x1: [ NextValue(bus_slv.dat_r, Cat(writ_ctr[24:32], writ_ctr[16:24], writ_ctr[ 8:16], writ_ctr[ 0: 8])), ], + }), + NextValue(bus_slv.ack, 1), + ).Else( + NextValue(bus_slv.ack, 0), + ) + ) diff --git a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py index 79c1891..cdaa012 100644 --- a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py +++ b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py @@ -18,6 +18,7 @@ import nubus_to_fpga_export import nubus import nubus_full +import nubus_stat from litedram.modules import MT41J128M16 from litedram.phy import s7ddrphy @@ -205,6 +206,7 @@ class NuBusFPGA(SoCCore): "goblin_bt" : 0xF0900000, # BT for goblin (regs) "goblin_accel" : 0xF0901000, # accel for goblin (regs) "goblin_accel_ram" : 0xF0902000, # accel for goblin (scratch ram) + "stat" : 0xF0903000, # stat "goblin_accel_rom" : 0xF0910000, # accel for goblin (rom) "csr" : 0xF0A00000, # CSR "pingmaster": 0xF0B00000, @@ -327,6 +329,10 @@ class NuBusFPGA(SoCCore): self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys) self.bus.add_slave("DMA", self.wishbone_slave_sys, SoCRegion(origin=self.mem_map.get("master", None), size=0x40000000, cached=False)) self.bus.add_master(name="NuBusBridgeToWishboneWrite", master=nubus_writemaster_sys) + + self.submodules.stat = nubus_stat.NuBusStat(nubus=self.nubus, platform=platform) + self.bus.add_slave("Stat", self.stat.bus_slv, SoCRegion(origin=self.mem_map.get("stat", None), size=0x1000, cached=False)) + if (goblin): if (not hdmi):