diff --git a/nubus-to-ztex-gateware/DeclROM/gen_mode.c b/nubus-to-ztex-gateware/DeclROM/gen_mode.c index 64c9352..af8c4a1 100644 --- a/nubus-to-ztex-gateware/DeclROM/gen_mode.c +++ b/nubus-to-ztex-gateware/DeclROM/gen_mode.c @@ -269,7 +269,7 @@ int main(int argc, char **argv) { fprintf(fd, "\tOSLstEntry\tsRsrc_GoboFB_R%hux%hu,_sRsrc_GoboFB_R%hux%hu/* video sRsrc List */\n", hres, vres, hres, vres); } } - //fprintf(fd, "\tOSLstEntry\tsRsrc_RAMDsk,_sRsrc_RAMDsk\n"); + fprintf(fd, "\tOSLstEntry\tsRsrc_RAMDsk,_sRsrc_RAMDsk\n"); fprintf(fd, "\tOSLstEntry\tsRsrc_HDMIAudio,_sRsrc_HDMIAudio\n"); fprintf(fd, "\tDatLstEntry endOfList, 0\n"); diff --git a/nubus-to-ztex-gateware/do_V1.2 b/nubus-to-ztex-gateware/do_V1.2 index fd8f5dc..cfc5e48 100644 --- a/nubus-to-ztex-gateware/do_V1.2 +++ b/nubus-to-ztex-gateware/do_V1.2 @@ -2,7 +2,7 @@ source /opt/Xilinx/Vivado/2020.1/settings64.sh export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE -python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi --ethernet +python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi # --ethernet #python3 nubus_to_fpga_soc.py --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 diff --git a/nubus-to-ztex-gateware/nubus_full_unified.py b/nubus-to-ztex-gateware/nubus_full_unified.py index 51c6a6f..fb8d156 100644 --- a/nubus-to-ztex-gateware/nubus_full_unified.py +++ b/nubus-to-ztex-gateware/nubus_full_unified.py @@ -699,13 +699,15 @@ class NuBus(Module): nub_adn = platform.request("ad_3v3_n") # V1.0: from CPLD ; V1.2: from shifters nub_idn = platform.request("id_3v3_n") # V1.0: from CPLD (4 bits) ; V1.2: from shifters (3 bits, /ID3 is always 0) + # idem between V1.0 and V1.2 + self.specials += Tristate(nub_adn, ad_o_n, ad_oe, ad_i_n) + # Tri-state if (version == "V1.0"): # tri-state communication with CPLD self.specials += Tristate(nub_tm0n, tm0_o_n, tmo_oe, tm0_i_n) self.specials += Tristate(nub_tm1n, tm1_o_n, tmo_oe, tm1_i_n) self.specials += Tristate(nub_ackn, ack_o_n, tmo_oe, ack_i_n) - self.specials += Tristate(nub_adn, ad_o_n, ad_oe, ad_i_n) self.specials += Tristate(nub_startn, start_o_n, master_oe, start_i_n) elif (version == "V1.2"): # input only @@ -713,7 +715,6 @@ class NuBus(Module): tm0_i_n.eq(nub_tm0n), tm1_i_n.eq(nub_tm1n), ack_i_n.eq(nub_ackn), - ad_i_n.eq(nub_adn), start_i_n.eq(nub_startn), ] else: @@ -765,6 +766,7 @@ class NuBus(Module): nf_grant = platform.request("grant") # V1.0: from cpld nf_nubus_master_dir = platform.request("nubus_master_dir") # V1.0: to cpld nf_fpga_to_cpld_signal = platform.request("fpga_to_cpld_signal") # V1.0: to cpld, 'rqstoen' + # NuBus90 signals, , for completeness nub_clk2xn = ClockSignal(cd_nubus90) @@ -779,9 +781,8 @@ class NuBus(Module): ] if (version == "V1.2"): - self.nubus_oe = nubus_oe = Signal() # improveme self.specials += Instance("nubus_cpldinfpga", - i_nubus_oe = nubus_oe, # improveme: handled in soc + i_nubus_oe = soc.hold_reset, # improveme, handled in SoC i_tmoen = ~tmo_oe, i_nubus_master_dir = master_oe, i_rqst_oe_n = ~rqst_oe, diff --git a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py index 6c5975a..d8dcf12 100644 --- a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py +++ b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py @@ -84,9 +84,10 @@ class _CRG(Module): if (version == "V1.2"): self.clock_domains.cd_bank34 = ClockDomain() clk54 = platform.request("clk54") + platform.add_platform_command("create_clock -name clk54 -period 18.51851851851851851 [get_nets clk54]") self.clk54_bufg = Signal() self.specials += Instance("BUFG", i_I=clk54, o_O=self.clk54_bufg) - self.comb += self.cd_native.clk.eq(self.clk54_bufg) + self.comb += self.cd_bank34.clk.eq(self.clk54_bufg) else: clk54 = None @@ -334,7 +335,7 @@ class NuBusFPGA(SoCCore): #hold_reset_ctr = Signal(30, reset=960000000) hold_reset_ctr = Signal(5, reset=31) self.sync.native += If(hold_reset_ctr>0, hold_reset_ctr.eq(hold_reset_ctr - 1)) - hold_reset = Signal() + self.hold_reset = hold_reset = Signal() # in reset if high, out-of-reset if low self.comb += hold_reset.eq(~(hold_reset_ctr == 0)) pad_nubus_oe = platform.request("nubus_oe") self.comb += pad_nubus_oe.eq(hold_reset) diff --git a/nubus-to-ztex-gateware/ztex213_nubus.py b/nubus-to-ztex-gateware/ztex213_nubus.py index 5d6e1bd..bbfce56 100644 --- a/nubus-to-ztex-gateware/ztex213_nubus.py +++ b/nubus-to-ztex-gateware/ztex213_nubus.py @@ -104,8 +104,8 @@ _nubus_io_v1_2 = [ ## extra 54 MHz clock reference for bank 34 ("clk54", 0, Pins("R3"), IOStandard("LVCMOS33")), ## leds on the NuBus board - ("user_led", 0, Pins("U9"), IOStandard("lvcmos33")), #LED0 - ("user_led", 1, Pins("V9"), IOStandard("lvcmos33")), #LED1; both are overlapping with serial TX/RX + ("user_led", 0, Pins("V9"), IOStandard("lvcmos33")), #LED0 + ("user_led", 1, Pins("U9"), IOStandard("lvcmos33")), #LED1; both are overlapping with serial TX/RX ## serial header for console ("serial", 0, Subsignal("tx", Pins("V9")), # FIXME: might be the other way round